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31. 发明授权

US08791526B2 Vertical type integrated circuit devices and memory devices including conductive lines supported by Mesa structures and methods of fabricating the same 有权
标题翻译：包括由Mesa结构支撑的导电线的垂直型集成电路器件和存储器件及其制造方法
公开(公告)号：US08791526B2
公开(公告)日：2014-07-29
申请号：US12891910
申请日：2010-09-28
申请人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
发明人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
IPC分类号： H01L29/66
CPC分类号： H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
摘要翻译：垂直型集成电路装置包括基板和从基板垂直突出的支柱。支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。还讨论了相关装置和制造方法。

32. 发明申请

US20080185641A1 Recessed transistor and method of manufacturing the same 有权
标题翻译：嵌入式晶体管及其制造方法
公开(公告)号：US20080185641A1
公开(公告)日：2008-08-07
申请号：US12068179
申请日：2008-02-04
申请人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
发明人： Keun-Nam Kim , Makoto Yoshida , Chul Lee , Dong-Gun Park , Woun-Suck Yang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/66621 , H01L29/7834 , H01L29/7851
摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.
摘要翻译：提供凹陷晶体管及其制造方法。凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。衬底可以包括建立衬底的有源区和场区的隔离层。衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。源/漏区可以与有源区和栅电极相邻形成。

33. 发明申请

US20110095350A1 VERTICAL TYPE INTEGRATED CIRCUIT DEVICES, MEMORY DEVICES, AND METHODS OF FABRICATING THE SAME 有权
标题翻译：垂直型集成电路装置，存储装置及其制造方法
公开(公告)号：US20110095350A1
公开(公告)日：2011-04-28
申请号：US12891910
申请日：2010-09-28
申请人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
发明人： Jae-man Yoon , Hyeong-sun Hong , Kwang-youl Chun , Makoto Yoshida , Deok-sung Hwang , Chul Lee
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10897 , H01L27/105 , H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L29/0657 , H01L29/42356 , H01L29/66666 , H01L29/7827
摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.
摘要翻译：垂直型集成电路装置包括基板和从基板垂直突出的支柱。支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。还讨论了相关装置和制造方法。

34. 发明授权

US08502341B2 Trench-type capacitor, semiconductor device having the same, and semiconductor module having the semiconductor device 有权
标题翻译：沟槽型电容器，具有该沟槽型电容器的半导体器件和具有半导体器件的半导体模块
公开(公告)号：US08502341B2
公开(公告)日：2013-08-06
申请号：US13021333
申请日：2011-02-04
申请人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
发明人： Chul Lee , Hyeong-Sun Hong , Deok-Sung Hwang , Jae-Man Yoon , Bong-Soo Kim
IPC分类号： H01L29/92
CPC分类号： H01L29/92
摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.
摘要翻译：提供了沟槽型电容器。为了形成电容器，第一和第二有源区域设置在半导体衬底中。节点图案设置在第一活动区域中。每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。杂质扩散区域设置在节点图案附近。设置与第一和第二有源区电接触的衬底连接图案。与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

35. 发明授权

US07227220B2 Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
标题翻译：具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法
公开(公告)号：US07227220B2
公开(公告)日：2007-06-05
申请号：US11240544
申请日：2005-09-30
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

36. 发明申请

US20070042582A1 Method of forming a nanowire and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成纳米线的方法和使用该纳米线的半导体器件的制造方法
公开(公告)号：US20070042582A1
公开(公告)日：2007-02-22
申请号：US11431216
申请日：2006-05-10
申请人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
发明人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/465
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y30/00 , H01L29/0665 , H01L29/0673 , Y10S977/938
摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.
摘要翻译：在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。在衬底上形成绝缘层图案以填充沟槽。绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。通过用绝缘层图案蚀刻衬底的暴露部分形成开口。在开口和绝缘层图案的侧壁上形成间隔物。连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出来形成。

37. 发明申请

US20060131613A1 Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines 失效
标题翻译：具有掩埋位线的半导体器件和具有掩埋位线的半导体器件的制造方法
公开(公告)号：US20060131613A1
公开(公告)日：2006-06-22
申请号：US11240544
申请日：2005-09-30
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L27/10
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

38. 发明申请

US20070190725A1 Methods of Manufacturing Semiconductor devices Having Buried Bit Lines 审中-公开
标题翻译：制造埋置位线的半导体器件的方法
公开(公告)号：US20070190725A1
公开(公告)日：2007-08-16
申请号：US11740525
申请日：2007-04-26
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

39. 发明授权

US07410853B2 Method of forming a nanowire and method of manufacturing a semiconductor device using the same 有权
标题翻译：形成纳米线的方法和使用该纳米线的半导体器件的制造方法
公开(公告)号：US07410853B2
公开(公告)日：2008-08-12
申请号：US11431216
申请日：2006-05-10
申请人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
发明人： Young-Joon Ahn , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/3083 , B82Y10/00 , B82Y30/00 , H01L29/0665 , H01L29/0673 , Y10S977/938
摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.
摘要翻译：在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。在衬底上形成绝缘层图案以填充沟槽。绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。通过用绝缘层图案蚀刻衬底的暴露部分形成开口。在开口和绝缘层图案的侧壁上形成间隔物。连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出而形成。

40. 发明公开

US20230230671A1 HEALTH TRACKING SYSTEM WITH VERIFICATION OF NUTRITION INFORMATION 审中-公开
公开(公告)号：US20230230671A1
公开(公告)日：2023-07-20
申请号：US17992424
申请日：2022-11-22
申请人： Chul Lee , Hesamoddin Salehian
发明人： Chul Lee , Hesamoddin Salehian
IPC分类号： G16H20/60 , G06F7/36 , G16H50/30 , G16H10/60
CPC分类号： G16H20/60 , G06F7/36 , G16H50/30 , G16H10/60
摘要： A method for decreasing a number of individual entries in a database of user-created records which describe a single item by: receiving a plurality of user-created records, each of said records comprising at least a descriptive string; placing individual ones of the plurality of user-created records having a sufficiently similar descriptive string into one of a plurality of first groups; hashing the descriptive string of each of the plurality of first groups in order to place two or more groups into a single bin; performing a pair-wise comparison of the descriptive strings of the two or more groups in each bin; and when the comparison of the descriptive strings of the two or more groups in a bin results in a distance below a first threshold, merging the two or more groups into a combined group.

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