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31. 发明授权

US06121146A Method for forming contact plugs of a semiconductor device 失效
标题翻译：用于形成半导体器件的接触插塞的方法
公开(公告)号：US06121146A
公开(公告)日：2000-09-19
申请号：US92021
申请日：1998-06-05
申请人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
发明人： Bo-Un Yoon , In-Kwon Jeong , Won-Seong Lee
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3105 , H01L21/321 , H01L21/768
CPC分类号： H01L21/7684 , H01L21/76819 , H01L21/31053 , H01L21/3212
摘要： A method for forming contact plugs of a semiconductor device includes a step of forming a conductive layer on an insulating layer filling up a contact hole. The method further comprises a step of planarization-etching an upper surface of the insulating layer as well as the contact plugs, after formation of the contact plugs by etching the conductive layer using an etch-back or a CMP process until at least the upper surface of the insulating layer is exposed. Alternatively, the conductive and insulating layers are simultaneously planarization-etched using a CMP process once to form the contact plugs and planarize the upper surface of the insulating layer. With this method, a bridge between interconnections which can be generated due to a scratch of the upper surface of the insulating layer can be prevented by planarization-etching the conductive layer after filling up a contact hole with the conductive layer. Also, since the insulating layer includes a lower insulating layer and an upper insulating layer having a relatively high hardness to the lower insulating layer, high-step and low-step regions of the insulating layer formed along topology of a gate electrode or a metal interconnection are efficiently planarized. As a result, a thickness of the insulating layer can be considerably reduced.
摘要翻译：用于形成半导体器件的接触插塞的方法包括在填充接触孔的绝缘层上形成导电层的步骤。该方法还包括在通过使用回蚀刻或CMP工艺蚀刻导电层形成接触插塞之后，平坦化 - 蚀刻绝缘层的上表面以及接触插塞的步骤，直到至少上表面的绝缘层露出。或者，使用CMP处理同时对导电绝缘层进行平面蚀刻，以形成接触插塞并平坦化绝缘层的上表面。利用该方法，可以通过在与导电层填充接触孔之后对导电层进行平坦化蚀刻来防止由于绝缘层的上表面的划痕而产生的互连之间的桥。此外，由于绝缘层包括下绝缘层和对下绝缘层具有相对较高硬度的上绝缘层，所以沿着栅电极或金属互连的拓扑形成绝缘层的高阶段和低阶区有效地平坦化。结果，绝缘层的厚度可以大大降低。

32. 发明授权

US08916460B1 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08916460B1
公开(公告)日：2014-12-23
申请号：US14270315
申请日：2014-05-05
申请人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
发明人： Byoung-Ho Kwon , Cheol Kim , Ho-Young Kim , Se-Jung Park , Myeong-Cheol Kim , Bo-Kyeong Kang , Bo-Un Yoon , Jae-Kwang Choi , Si-Young Choi , Suk-Hoon Jeong , Geum-Jung Seong , Hee-Don Jeong , Yong-Joon Choi , Ji-Eun Han
IPC分类号： H01L29/49 , H01L29/78 , H01L21/336 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7853 , H01L21/30604 , H01L21/3065 , H01L21/3085 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0886 , H01L27/1211 , H01L29/0673 , H01L29/42364 , H01L29/4238 , H01L29/49 , H01L29/66545 , H01L29/6656 , H01L29/66795 , H01L29/78 , H01L29/785
摘要： Semiconductor devices may include a semiconductor substrate with a first semiconductor fin aligned end-to-end with a second semiconductor with a recess between facing ends of the first and second semiconductor fins. A first insulator pattern is formed adjacent sidewalls of the first and second semiconductor fins and a second insulator pattern is formed within the first recess. The second insulator pattern may have a top surface higher than a top surface of the first insulator pattern, such as to the height of the top surface of the fins (or higher or lower). First and second gates extend along sidewalls and a top surface of the first semiconductor fin. A dummy gate electrode may be formed on the top surface of the second insulator. Methods for manufacture of the same and modifications are also disclosed.
摘要翻译：半导体器件可以包括具有第一半导体鳍片的半导体衬底，第一半导体鳍片端对端与第二半导体对准，第二半导体在第一和第二半导体鳍片的相对端之间具有凹陷。第一绝缘体图案形成在第一和第二半导体鳍片的相邻侧壁附近，并且在第一凹部内形成第二绝缘体图案。第二绝缘体图案可以具有高于第一绝缘体图案的顶表面的顶表面，例如高于鳍片（或更高或更低）的顶表面的高度。第一和第二栅极沿第一半导体鳍片的侧壁和顶表面延伸。可以在第二绝缘体的顶表面上形成伪栅电极。还公开了其制造方法和修改方案。

33. 发明授权

US08557651B2 Method of manufacturing a semiconductor device using an etchant 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US08557651B2
公开(公告)日：2013-10-15
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/8238
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

34. 发明授权

US08344385B2 Vertical-type semiconductor device 有权
标题翻译：垂直型半导体器件
公开(公告)号：US08344385B2
公开(公告)日：2013-01-01
申请号：US12872270
申请日：2010-08-31
申请人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
发明人： Young-Hoo Kim , Hyo-San Lee , Sang-Won Bae , Bo-Un Yoon , Kun-Tack Lee
IPC分类号： H01L29/06 , H01L29/792
CPC分类号： H01L27/11578 , H01L27/11556 , H01L27/11582
摘要： In a vertical-type non-volatile memory device, an insulation layer pattern is provided on a substrate, the insulation layer pattern having a linear shape. Single-crystalline semiconductor patterns are provided on the substrate to make contact with both sidewalls of the insulation layer pattern, the single-crystalline semiconductor patterns having a pillar shape that extends in a vertical direction relative to the substrate. A tunnel oxide layer is provided on the single-crystalline semiconductor pattern. A lower electrode layer pattern is provided on the tunnel oxide layer and on the substrate. A plurality of insulation interlayer patterns is provided on the lower electrode layer pattern, the insulation interlayer patterns being spaced apart from one another by a predetermined distance along the single-crystalline semiconductor pattern. A charge-trapping layer and a blocking dielectric layer are sequentially formed on the tunnel oxide layer between the insulation interlayer patterns. A plurality of control gate patterns is provided on the blocking dielectric layer between the insulation interlayer patterns. An upper electrode layer pattern is provided on the tunnel oxide layer and on the uppermost insulation interlayer pattern.
摘要翻译：在垂直型非易失性存储器件中，在衬底上设置绝缘层图案，绝缘层图案具有直线形状。单晶半导体图案设置在基板上以与绝缘层图案的两个侧壁接触，单晶半导体图案具有相对于基板在垂直方向上延伸的柱状。隧道氧化物层设置在单晶半导体图案上。在隧道氧化物层和衬底上提供下电极层图案。在下电极层图案上设置多个绝缘层间图案，绝缘层间图案沿着单晶半导体图案彼此隔开预定距离。在绝缘层间图案之间的隧道氧化物层上依次形成电荷捕获层和阻挡介质层。在绝缘夹层图案之间的阻挡介质层上设置多个控制栅极图案。在隧道氧化物层和最上层的绝缘层间图案上设置上电极层图案。

35. 发明授权

US08211804B2 Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole 有权
标题翻译：形成具有垂直剖面的孔的方法和具有垂直孔的半导体器件
公开(公告)号：US08211804B2
公开(公告)日：2012-07-03
申请号：US13025410
申请日：2011-02-11
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Dae-Hyuk Kang , Seong-Ho Moon , So-Ra Han
IPC分类号： H01L21/311
CPC分类号： H01L21/31111 , H01L21/32134 , H01L21/76802 , H01L27/10852 , H01L27/10876 , H01L27/10894 , H01L27/11578 , H01L27/11582 , H01L28/91 , H01L29/4236 , H01L29/66621 , H01L29/66833 , H01L29/7926
摘要： In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
摘要翻译：在形成孔的方法中，在基板上形成绝缘层，通过绝缘层形成露出基板的预备孔。然后在基板上形成包含有机聚合物的感光层图案以填充预备孔。然后将包含氟化氢（HF）或氟（F2）的蚀刻气体提供到感光层图案上以蚀刻绝缘层，使得预备孔的宽度增加。

36. 发明授权

US08119476B2 Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby 有权
标题翻译：形成具有侧壁支撑件的集成电路电容器和由此形成的电容器的方法
公开(公告)号：US08119476B2
公开(公告)日：2012-02-21
申请号：US12906184
申请日：2010-10-18
申请人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
发明人： Dae-Hyuk Kang , Bo-Un Yoon , Kun-Tack Lee , Woo-Gwan Shim , Ji-Hoon Cha , Im-Soo Park , Hyo-San Lee , Young-Hoo Kim , Jung-Min Oh
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852 , H01L28/87
摘要： In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
摘要翻译：在形成电容器的方法中，可以在基板上形成包括第一绝缘材料的第一模层图案。第一模层图案可以具有沟槽。可以在沟槽中形成包括第二绝缘材料的支撑层。第二绝缘材料可以具有相对于第一绝缘材料的蚀刻选择性。可以在第一模层图案和支撑层图案上形成第二模层。可以通过第二模具层和第一模具层图案形成下部电极。下电极可以与支撑层图案的侧壁接触。可以去除第一模层图案和第二模层。电介质层和上电极可以形成在下电极和支撑层图案上。

37. 发明申请

US20110217833A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING AN ETCHANT 有权
标题翻译：使用蚀刻剂制造半导体器件的方法
公开(公告)号：US20110217833A1
公开(公告)日：2011-09-08
申请号：US13040472
申请日：2011-03-04
申请人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
发明人： Hyo-San Lee , Bo-Un Yoon , Kun-Tack Lee , Hag-Ju Cho , Sang-Jin Hyun , Hoon-Joo Na , Hyung-Seok Hong
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.
摘要翻译：在蚀刻具有相对于电介质层的蚀刻选择性的封盖层的蚀刻剂中，封盖层改变介电层的组成，从而控制包括电介质层的栅电极的阈值电压。蚀刻剂包括约0.01至3重量％的酸，约10至40重量％的氟化物盐和溶剂。因此，通过用于去除封盖层的蚀刻工艺来防止电介质层损坏，并且提高了栅电极的电特性。

38. 发明授权

US07781281B2 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US07781281B2
公开(公告)日：2010-08-24
申请号：US12694715
申请日：2010-01-27
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

39. 发明申请

US20090155991A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090155991A1
公开(公告)日：2009-06-18
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

40. 发明申请

US20070072407A1 Method of fabricating self-aligned contact pad using chemical mechanical polishing process 有权
标题翻译：使用化学机械抛光工艺制造自对准接触垫的方法
公开(公告)号：US20070072407A1
公开(公告)日：2007-03-29
申请号：US11525490
申请日：2006-09-23
申请人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
发明人： Ho-Young Kim , Chang-Ki Hong , Bo-Un Yoon , Joon-Sang Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/7684 , H01L27/10873 , H01L27/10885
摘要： A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks. The method further includes etching the portion of the insulation layer exposed by the opening region using the first and second etching masks to form a plurality of opening holes, removing the second etching mask, forming a conductive layer filling the opening holes to cover the remaining first etching masks and performing a chemical mechanical polishing (CMP) process on the conductive layer using the capping layer as a polishing end point to remove the first etching masks such that a plurality of SAC pads separated from each other are formed that fill the opening holes.
摘要翻译：一种制造自对准接触焊盘（SAC）的方法包括在半导体衬底上形成导电线和覆盖层的叠层，覆盖堆叠的侧壁的间隔物和填充堆叠之间的间隙的绝缘层，覆盖层，蚀刻覆盖层以形成镶嵌槽，用不同于覆盖层的材料形成多个第一蚀刻掩模以填充镶嵌槽而不覆盖绝缘层的顶部，以及形成第二蚀刻掩模具有暴露一些第一蚀刻掩模的开口区域和位于第一蚀刻掩模之间的绝缘层的一部分。该方法还包括使用第一和第二蚀刻掩模蚀刻由开口区域暴露的绝缘层的部分，以形成多个开孔，去除第二蚀刻掩模，形成填充开孔的导电层以覆盖剩余的第一蚀刻掩模并使用覆盖层作为抛光终点在导电层上进行化学机械抛光（CMP）工艺，以去除第一蚀刻掩模，从而形成填充开孔的彼此分离的多个SAC焊盘。

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