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31. 发明申请

US20050167741A1 ENCAPSULATED SPACERS IN VERTICAL PASS GATE DRAM AND DAMASCENE LOGIC GATES 失效
标题翻译：垂直通道门和大气门逻辑门的封装间隔
公开(公告)号：US20050167741A1
公开(公告)日：2005-08-04
申请号：US10770264
申请日：2004-02-02
申请人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
发明人： Ramachandra Divakaruni , Stephan Kudelka , Jack Mandelman
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/06 , H01L29/423 , H01L29/737 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66537 , H01L21/28114 , H01L27/10864 , H01L27/10876 , H01L27/10891 , H01L29/0692 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7371 , H01L29/7834
摘要： Semiconductor devices having improved isolation are provided along with methods of fabricating such semiconductor devices. The improved isolation includes an encapsulated spacer formed within a gate region of a device.
摘要翻译：提供具有改进的隔离的半导体器件与制造这种半导体器件的方法一起提供。改进的隔离包括形成在器件的栅极区域内的封装间隔物。

32. 发明授权

US06548344B1 Spacer formation process using oxide shield 有权
标题翻译：隔板形成工艺采用氧化物屏蔽
公开(公告)号：US06548344B1
公开(公告)日：2003-04-15
申请号：US09987956
申请日：2001-11-16
申请人： Jochen Beintner , Stephan Kudelka , Thomas Dyer
发明人： Jochen Beintner , Stephan Kudelka , Thomas Dyer
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10888 , H01L27/10891
摘要： In the formation of a semiconductor structure, where spacer formation is strongly dependent on the structure (e.g. taper), the improvement of a spacer formation on a poly stud planarized to pad nitride where an oxide is formed on top of the poly prior to the pad nitride strip, so that after pad nitride removal, the poly is etched back and nitride is deposited conformal followed by anisotropic nitride RIE etch, so that the oxide protects the nitride underneath from being etched.
摘要翻译：在半导体结构的形成中，其中间隔物形成强烈地取决于结构（例如锥形），改善在平坦化为衬垫氮化物的多晶硅柱上的间隔物形成，其中在衬垫之前在聚氨酯的顶部上形成氧化物氮化物条，使得在去除衬垫氮化物之后，将多晶硅回蚀刻，并且将氮化物保形共形，随后进行各向异性氮化物RIE蚀刻，使得氧化物保护下方的氮化物免受蚀刻。

33. 发明授权

US06295998B1 Temperature controlled gassification of deionized water for megasonic cleaning of semiconductor wafers 失效
标题翻译：用于超声波清洗半导体晶片的去离子水的温度控制气化
公开(公告)号：US06295998B1
公开(公告)日：2001-10-02
申请号：US09318155
申请日：1999-05-25
申请人： Stephan Kudelka , David Rath
发明人： Stephan Kudelka , David Rath
IPC分类号： B08B312
CPC分类号： H01L21/02052 , B08B3/04 , B08B3/12
摘要： A system is provided to prepare deionized water having a 100% saturated concentration of a gas, e.g., nitrogen, at a hot temperature, e.g., 50-85° C., and an attendant pressure, e.g., atmospheric pressure, to clean a semiconductor wafer, e.g., of silicon. The gas concentration of a first deionized water portion having a predetermined concentration of the gas at a cold temperature, e.g., 20-30° C., is adjusted in a gassifier chamber having a pressure pump and a pressure sensor, to provide a predetermined under-saturated concentration of the gas at the cold temperature. The temperature of the adjusted gas concentration first water portion is then adjusted by mixing therewith a second deionized water portion having a predetermined concentration of the gas at a predetermined very hot temperature, e.g., 80° C., in a predetermined ratio in a mixer having a temperature sensor. The flows of the first and second water portions are controlled by first and second flow controllers, to form a hot bath at the hot temperature having such saturated gas concentration to clean the wafer, e.g., in a cleaning tank under megasonic vibrations. A controller is connected to the pump, pressure sensor, temperature sensor and first and second flow controllers to control the chamber pressure and the operation of the flow controllers.
摘要翻译：提供一种系统来制备具有100％饱和浓度的气体（例如氮气）的去离子水，其在例如50-85℃的热温度和伴随的压力（例如大气压）下清洁半导体晶片，例如硅。在具有压力泵和压力传感器的放气室中调节在例如20-30℃的冷温度下具有预定浓度气体的第一去离子水部分的气体浓度，以提供预定的下在低温下气体的饱和浓度。然后通过混合具有预定浓度气体的第二去离子水部分的调节气体浓度第一水部分的温度，所述第二去离子水部分在预定的非常热的温度（例如80℃）下以预定比例在具有温度传感器。第一和第二水部分的流动由第一和第二流量控制器控制，以在具有这种饱和气体浓度的热温下形成热浴，以清洁晶片，例如在超声波振动下的清洗槽中。控制器连接到泵，压力传感器，温度传感器和第一和第二流量控制器，以控制腔室压力和流量控制器的操作。

34. 发明授权

US07413951B2 Stacked capacitor and method for producing stacked capacitors for dynamic memory cells 失效
标题翻译：叠层电容器和用于制造用于动态存储单元的叠层电容器的方法
公开(公告)号：US07413951B2
公开(公告)日：2008-08-19
申请号：US11518504
申请日：2006-09-07
申请人： Stephan Kudelka , Peter Moll , Stefan Jakschik , Odo Wunnicke
发明人： Stephan Kudelka , Peter Moll , Stefan Jakschik , Odo Wunnicke
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852
摘要： A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.
摘要翻译：一种方法产生用于动态存储单元的堆叠电容器，其中在掩模层（40）中形成有多个沟槽（48），每个沟槽（48）布置在相应的接触插塞（26）的上方并从顶部屏蔽层（40）的至少部分（42）连接到接触插塞（26）。为了形成叠层电容器（12）的第一电极（60），导电层（50）覆盖沟槽（48）的侧壁（49）和接触插塞（26）。在远离接触堆叠（26）的上部区域（63）中，导电层（50）由绝缘层代替，使得在任何粘附的情况下不可能出现短路在相邻电极之间。

35. 发明申请

US20080173917A1 Selective deposition method 审中-公开
标题翻译：选择性沉积法
公开(公告)号：US20080173917A1
公开(公告)日：2008-07-24
申请号：US11655664
申请日：2007-01-19
申请人： Matthias Patz , Alexey Ivanov , Stephan Kudelka
发明人： Matthias Patz , Alexey Ivanov , Stephan Kudelka
IPC分类号： H01L27/108 , H01L21/334
CPC分类号： H01L29/66181 , H01L27/1087
摘要： The invention relates to a deposition method performing the following steps. A substrate is provided which is structured to comprise a first surface and a second surface, which differ in at least one of geometric orientation and vertical distance to a principle surface of the substrate. An etchable layer is deposited on the first surface via an atomic layer deposition technique the deposition technique using a first precursor supplied in an amount sufficient to cover at least parts of the first surface and insufficient to cover the second surface, the first precursor being supplied from a direction to pass the first surface before the second surface. A dielectric layer of at least one of a transition metal oxide and a transition metal nitride is deposited on at least the second surface via an atomic layer deposition technique using a second precursor.
摘要翻译：本发明涉及一种执行以下步骤的沉积方法。提供了一种衬底，其被构造成包括第一表面和第二表面，所述第一表面和第二表面在基底的主要表面的几何取向和垂直距离中的至少一个方面不同。可蚀刻层通过原子层沉积技术沉积在第一表面上，沉积技术使用以足以覆盖第一表面的至少一部分并且不足以覆盖第二表面的量供应的第一前体，第一前体从在第二表面之前通过第一表面的方向。过渡金属氧化物和过渡金属氮化物中的至少一种的电介质层通过使用第二前体的原子层沉积技术沉积在至少第二表面上。

36. 发明授权

US07189614B2 Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact 失效
标题翻译：一种用于制造沟槽结构的方法，所述沟槽结构通过埋入触点一端电连接到衬底
公开(公告)号：US07189614B2
公开(公告)日：2007-03-13
申请号：US10886053
申请日：2004-07-08
申请人： Stephan Kudelka , Albrecht Kieslich , Kevin Pears
发明人： Stephan Kudelka , Albrecht Kieslich , Kevin Pears
IPC分类号： H01L21/8242
CPC分类号： H01L21/76895 , H01L27/10867
摘要： A method for fabricating a trench structure, in particular a trench capacitor with an insulation collar, which is electrically connected to a substrate on one side via a buried contact. Fabrication includes, for example, providing a trench in the substrate using a hard mask with a corresponding mask opening; providing an at least partial trench filling; providing a liner on the resulting structure; carrying out an oblique implantation of impurity ions onto the liner for altering the etching properties of an implanted partial region of the liner; selectively removing the implanted partial region of the liner by a first etching for forming a liner mask from the complimentary partial region of the liner, which partially masks the top side of the trench filling; removing a part of the trench filling by a second etching using the liner mask; and replacing the removed part of the trench filling.
摘要翻译：一种用于制造沟槽结构的方法，特别是具有绝缘套环的沟槽电容器，其通过埋入触点电连接到一侧的衬底。制造包括例如使用具有相应的掩模开口的硬掩模在衬底中提供沟槽; 提供至少部分沟槽填充; 在所得结构上提供衬垫; 将杂质离子倾斜地注入到衬垫上，以改变衬垫的注入部分区域的蚀刻性能; 通过第一蚀刻选择性地去除衬垫的注入部分区域，用于从衬垫的互补部分区域形成衬垫掩模，其部分地掩盖沟槽填充物的顶侧; 使用所述衬垫掩模通过第二蚀刻去除所述沟槽填充的一部分; 并更换去除的沟槽填充部分。

37. 发明申请

US20070007624A1 Method for fabricating a capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US20070007624A1
公开(公告)日：2007-01-11
申请号：US11179052
申请日：2005-07-11
申请人： Christian Kapteyn , Stephan Kudelka , Thomas Hecht
发明人： Christian Kapteyn , Stephan Kudelka , Thomas Hecht
IPC分类号： H01L29/00
CPC分类号： H01L28/40
摘要： The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.
摘要翻译：本发明涉及在半导体衬底中制造电容器的方法。电容器被制造成使得电容器包括：衬底内的沟槽，沟槽具有下部区域和上部区域，其中下部区域中的沟槽直径大于上部区域中的沟槽直径; 第一电极; 位于所述第一电极顶部的电介质层; 在所述电层顶部的导电层，所述导电层形成所述电容器的第二电极; 以及在下部区域内形成闭合腔的塞子。

38. 发明申请

US20050176256A1 Method for expanding a trench in a semiconductor structure 有权
标题翻译：用于在半导体结构中扩展沟槽的方法
公开(公告)号：US20050176256A1
公开(公告)日：2005-08-11
申请号：US11053668
申请日：2005-02-09
申请人： Stephan Kudelka
发明人： Stephan Kudelka
IPC分类号： H01L21/306 , H01L21/8242 , H01L21/76
CPC分类号： H01L21/30604 , H01L27/1087
摘要： The present invention provides a method for expanding a trench in a semiconductor structure. A trench is provided in a semiconductor substrate, hydrogen-terminated silicon surfaces are provided in the trench, anisotropic wet etching of the silicon surfaces in the trench with an alkaline etchant occur, and the trench is rinsed with a proton-containing neutralizing agent for the removal of the alkaline etchant. Between the wet etching step and the rinsing step, an anodic passivation of the etched silicon surfaces in the trench is carried out, in the course of which an etching stop layer is formed on the etched silicon surfaces in the trench.
摘要翻译：本发明提供了一种用于扩展半导体结构中的沟槽的方法。在半导体衬底中设置沟槽，在沟槽中设置氢封端的硅表面，发生在碱性蚀刻剂中的沟槽中的硅表面的各向异性湿蚀刻，并且用含质子的中和剂冲洗沟槽去除碱性蚀刻剂。在湿蚀刻步骤和漂洗步骤之间，在沟槽中进行蚀刻的硅表面的阳极钝化，在该过程中，在沟槽中蚀刻的硅表面上形成蚀刻停止层。

39. 发明申请

US20050176198A1 Method of fabricating bottle trench capacitors using an electrochemical etch with electrochemical etch stop 审中-公开
标题翻译：使用具有电化学蚀刻停止的电化学蚀刻来制造瓶槽电容器的方法
公开(公告)号：US20050176198A1
公开(公告)日：2005-08-11
申请号：US10775163
申请日：2004-02-11
申请人： Stephan Kudelka
发明人： Stephan Kudelka
IPC分类号： C25F3/12 , H01L21/20 , H01L21/3063 , H01L21/82 , H01L21/8242
CPC分类号： H01L27/1087 , C25F3/12 , H01L21/3063
摘要： A method of forming trench capacitors in, e.g., a DRAM device, using an electrochemical etch with built-in etch stop to fabricate well-defined bottle-shaped capacitors is described. The process includes formation of a sacrificial silicon layer after initial deep trench formation, wherein the sacrificial layer is formed by doping, and upon its removal, a bottle trench is formed. A second region of doped silicon located below the sacrificial layer is resistant to the chemical etch performed to remove the sacrificial layer, and thereby renders the bottle trench formation process self-limiting.
摘要翻译：描述了在例如DRAM器件中形成沟槽电容器的方法，其中使用具有内置蚀刻停止件的电化学蚀刻来制造明确定义的瓶形电容器。该过程包括在初始深沟槽形成之后形成牺牲硅层，其中牺牲层通过掺杂形成，并且在其去除时形成瓶沟槽。位于牺牲层下方的掺杂硅的第二区域对于去除牺牲层而进行的化学蚀刻是耐受的，从而使瓶形成沟槽形成过程是自限制的。

40. 发明授权

US06555430B1 Process flow for capacitance enhancement in a DRAM trench 失效
标题翻译： DRAM沟槽中电容增强的工艺流程
公开(公告)号：US06555430B1
公开(公告)日：2003-04-29
申请号：US09723420
申请日：2000-11-28
申请人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
发明人： Michael P. Chudzik , Johnathan Faltermeier , Rajarao Jammy , Stephan Kudelka , Irene McStay , Kenneth T. Settlemyer, Jr. , Helmut Horst Tews
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L28/84 , Y10S438/964
摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.
摘要翻译：提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

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