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31. 发明授权

US11544062B2 Apparatus and method for store pairing with reduced hardware requirements 有权
公开(公告)号：US11544062B2
公开(公告)日：2023-01-03
申请号：US16833596
申请日：2020-03-28
申请人： Intel Corporation
发明人： Raanan Sade , Igor Yanover , Stanislav Shwartsman , Muhammad Taher , David Zysman , Liron Zur , Yiftach Gilad
IPC分类号： G06F9/30 , G06F9/38 , G06F9/48 , G06F9/50
摘要： An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.

32. 发明授权

US11288069B2 Systems, methods, and apparatuses for tile store 有权
公开(公告)号：US11288069B2
公开(公告)日：2022-03-29
申请号：US16487755
申请日：2017-07-01
申请人： Intel Corporation
发明人： Robert Valentine , Menachem Adelman , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll , Milind B. Girkar , Zeev Sperber , Mark J. Charney , Rinat Rappoport , Jesus Corbal , Stanislav Shwartsman , Igor Yanover , Alexander F. Heinecke , Barukh Ziv , Dan Baum , Yuri Gebil
IPC分类号： G06F9/30 , G06F7/485 , G06F7/487 , G06F17/16 , G06F7/76 , G06F9/38
摘要： Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information

33. 发明授权

US11086623B2 Systems, methods, and apparatuses for tile matrix multiplication and accumulation 有权
公开(公告)号：US11086623B2
公开(公告)日：2021-08-10
申请号：US16487787
申请日：2017-07-01
申请人： Intel Corporation
发明人： Robert Valentine , Zeev Sperber , Mark J. Charney , Bret L. Toll , Rinat Rappoport , Stanislav Shwartsman , Dan Baum , Igor Yanover , Elmoustapha Ould-Ahmed-Vall , Menachem Adelman , Jesus Corbal , Yuri Gebil , Simon Rubanovich
IPC分类号： G06F9/30 , G06F7/485 , G06F7/487 , G06F17/16 , G06F7/76 , G06F9/38
摘要： Embodiments detailed herein relate to matrix operations. In particular, matrix (tile) multiply accumulate and negated matrix (tile) multiply accumulate are discussed. For example, in some embodiments decode circuitry to decode an instruction having fields for an opcode, an identifier for a first source matrix operand, an identifier of a second source matrix operand, and an identifier for a source/destination matrix operand; and execution circuitry to execute the decoded instruction to multiply the identified first source matrix operand by the identified second source matrix operand, add a result of the multiplication to the identified source/destination matrix operand, and store a result of the addition in the identified source/destination matrix operand and zero unconfigured columns of identified source/destination matrix operand are detailed.

34. 发明授权

US10754655B2 Automatic predication of hard-to-predict convergent branches 有权
公开(公告)号：US10754655B2
公开(公告)日：2020-08-25
申请号：US16021838
申请日：2018-06-28
申请人： Intel Corporation
发明人： Adarsh Chauhan , Hong Wang , Jayesh Gaur , Zeev Sperber , Sumeet Bandishte , Lihu Rappoport , Stanislav Shwartsman , Kamil Garifullin , Sreenivas Subramoney , Adi Yoaz
IPC分类号： G06F9/32 , G06F9/42 , G06F9/38 , G06F9/30
摘要： A processing device includes a branch IP table and branch predication circuitry coupled to the branch IP table. The branch predication circuitry to: determine a dynamic convergence point in a conditional branch of set of instructions; store the dynamic convergence point in the branch IP table; fetch a first and second speculative path of the conditional branch; while determining which of the first speculative path and the second speculative path is a taken path of the conditional branch and determining whether a dynamic convergence point is fetched corresponding to the stored dynamic convergence point, stall scheduling of instructions of the first speculative path and the second speculative path; and in response to determining that one of the first speculative path and the second speculative path is the taken path and the fetched dynamic convergence point corresponds to the stored convergence point, resume scheduling of the instructions of the taken path.

35. 发明授权

US10402263B2 Accelerating memory fault resolution by performing fast re-fetching 有权
公开(公告)号：US10402263B2
公开(公告)日：2019-09-03
申请号：US15831195
申请日：2017-12-04
申请人： Intel Corporation
发明人： Zeev Sperber , Stanislav Shwartsman , Jared W. Stark, IV , Lihu Rappoport , Igor Yanover , George Leifman
IPC分类号： G06F11/00 , G06F11/07 , G06F12/02 , G06F9/38 , G06F9/30
摘要： A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

36. 发明授权

US10152451B2 Scatter using index array and finite state machine 有权
公开(公告)号：US10152451B2
公开(公告)日：2018-12-11
申请号：US15490743
申请日：2017-04-18
申请人： Intel Corporation
发明人： Zeev Sperber , Robert Valentine , Shlomo Raikin , Stanislav Shwartsman , Gal Ofir , Igor Yanover , Guy Patkin , Ofer Levy
IPC分类号： G06F9/00 , G06F15/78 , G06F9/30 , G06F9/345 , G06F9/38
摘要： Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

37. 发明授权

US10146737B2 Gather using index array and finite state machine 有权
公开(公告)号：US10146737B2
公开(公告)日：2018-12-04
申请号：US14616323
申请日：2015-02-06
申请人： Intel Corporation
发明人： Zeev Sperber , Robert Valentine , Guy Patkin , Stanislav Shwartsman , Shlomo Raikin , Igor Yanover , Gal Ofir
IPC分类号： G06F9/00 , G06F15/80 , G06F9/30 , G06F9/38
摘要： Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

38. 发明申请

US20180137053A1 SEQUENTIAL DATA WRITES TO INCREASE INVALID TO MODIFIED PROTOCOL OCCURRENCES IN A COMPUTING SYSTEM 审中-公开
公开(公告)号：US20180137053A1
公开(公告)日：2018-05-17
申请号：US15352272
申请日：2016-11-15
申请人： INTEL CORPORATION
发明人： Pavel I. Kryukov , Stanislav Shwartsman , Joseph Nuzman , Alexandr Titov
IPC分类号： G06F12/0808 , G06F12/0811 , G06F12/0837 , G06F12/084 , G06F12/0842 , G06F12/0891
CPC分类号： G06F12/0808 , G06F12/0811 , G06F12/0833 , G06F12/0837 , G06F12/084 , G06F12/0842 , G06F12/0891 , G06F2212/1016 , G06F2212/1041 , G06F2212/502 , G06F2212/6042
摘要： An example system on a chip (SoC) includes a cache, a processor, and a predictor circuit. The cache may store data. The processor may be coupled to the cache and store a first data set at a first location in the cache and receive a first request from an application to write a second data set to the cache. The predictor circuit may be coupled to the processor and determine that a second location where the second data set is to be written to in the cache is nonconsecutive to the first location, where the processor is to perform a request-for-ownership (RFO) operation for the second data set and write the second data set to the cache.

39. 发明授权

US09904549B2 Method and apparatus for loop-invariant instruction detection and elimination 有权
公开(公告)号：US09904549B2
公开(公告)日：2018-02-27
申请号：US14998295
申请日：2015-12-26
申请人： Intel Corporation
发明人： Stanislav Shwartsman
IPC分类号： G06F9/30 , G06F12/0875
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30043 , G06F12/0875 , G06F2212/452
摘要： An apparatus and method for detecting and eliminating loop-invariant instructions. For example, one embodiment of a method comprises: detecting a loop start; responsively setting the loop-invariant bit for each register entry in a register alias table; executing first N iterations of the loop and responsively clearing the loop-invariant bit of any register modified during the first N iterations of the loop; identifying one or more loop-invariant registers based on the status of the loop-invariant bit in the register alias table; identifying one or more loop-invariant instructions based on the loop-invariant registers; and propagating the identified loop-invariant instructions by storing the destination register's values in a physical register file for later reuse by other instructions.

40. 发明授权

US09501132B2 Instruction and logic for store broadcast and power management 有权
标题翻译：商店广播和电源管理的指导和逻辑
公开(公告)号：US09501132B2
公开(公告)日：2016-11-22
申请号：US14453341
申请日：2014-08-06
申请人： Intel Corporation
发明人： Michael Mishaeli , Stanislav Shwartsman , Gal Ofir , Yulia Kurolap
IPC分类号： G06F1/32 , G06F9/30 , G06F15/78
CPC分类号： G06F1/3287 , G06F1/32 , G06F9/30145 , G06F15/7807 , Y02D10/171 , Y02D50/20
摘要： A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit. The decode unit includes logic to decode a store broadcast instruction of a specified width. The LPG includes logic to selectively provide power to the locally-gated circuitry, activate power to a first portion of the locally-gated circuitry for execution of full cache-line memory operations, and deactivate power to a second portion of the locally-gated circuitry the locally-gated circuitry. The execution unit includes logic to execute, by the first portion of the locally-gated circuitry for execution of full cache-line memory operations, the store broadcast instruction, the store broadcast instruction to store data of the specified width to storage of the processor.
摘要翻译：处理器包括具有本地门控电路的核心，解码单元，耦合到本地门控电路的本地电源门（LPG）以及执行单元。解码单元包括用于解码指定宽度的存储广播指令的逻辑。 LPG包括用于选择性地向本地门控电路提供电力的逻辑，激活本地门控电路的第一部分以执行完全高速缓存行存储器操作的功率，以及去激活局部门控电路的第二部分的功率本地门控电路。执行单元包括由用于执行全高速缓存行存储器操作的本地门控电路的第一部分执行存储广播指令，存储广播指令以存储指定宽度的数据以存储处理器的逻辑。

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