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31. 发明申请

US20050055481A1 FLASH DRIVE/READER WITH SERIAL-PORT CONTROLLER AND FLASH-MEMORY CONTROLLER MASTERING A SECOND RAM-BUFFER BUS PARALLEL TO A CPU BUS 失效
标题翻译：具有串行端口控制器和闪存控制器的闪存驱动器/读取器主机将第二个RAM缓冲器总线并行连接到CPU总线
公开(公告)号：US20050055481A1
公开(公告)日：2005-03-10
申请号：US10605140
申请日：2003-09-10
申请人： Horng-Yee Chou , Sun-Teck See , Tzu-Yih Chu
发明人： Horng-Yee Chou , Sun-Teck See , Tzu-Yih Chu
IPC分类号： G06F3/00 , G06F3/06 , G06F13/00 , G06F13/12 , G06F13/38 , G11C16/10
CPC分类号： G06F13/387 , G11C16/102
摘要： A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.
摘要翻译：闪存驱动器或闪存卡读卡器通过串行链路（例如通用串行总线（USB），IEEE 1394，SATA或IDE）连接到个人计算机（PC）。本地CPU作为连接闪存控制器，串行引擎和RAM缓冲区的从站端口的CPU总线的总线主机。与CPU总线并行的第二个总线将RAM缓冲器上的第二个从站端口连接到闪存控制器上的主站和串行引擎上的主站。闪存控制器或串行引擎可以使用其主端口使用第二个总线将数据传输到RAM缓冲区，并允许CPU保留对CPU总线的控制。第二个总线是提供数据传输速率的闪存串行缓冲区总线。闪存控制器可以预取入RAM缓冲区。

32. 发明授权

US5133074A Deadlock resolution with cache snooping 失效
标题翻译：具有缓存监听的死锁分辨率
公开(公告)号：US5133074A
公开(公告)日：1992-07-21
申请号：US308206
申请日：1989-02-08
申请人： Horng-Yee Chou
发明人： Horng-Yee Chou
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/524 , G06F12/0831
摘要： A device for resolving deadlock between a local processor and system resources for access to a local store in a multiprocessor data processing system having high speed cache comprises an address storage device, deadlock resolution logic and a deadlock detector. The address storage device is coupled to the local bus for storing addresses in response a local store access signal on the system bus and for supply of the address to the cache controller. The detector is connected to the local bus and system bus to detect a deadlock condition. The deadlock resolution logic generates a sequence of control signals in response to the deadlock signal that resolves the deadlock condition. In particular, deadlocks are resolved by tristating the local buffer in response to the deadlock signal to disable external access signals from controlling the local bus to allow a local store access signal to gain control of the local bus. If the local store access signal is a write access, the address of the write access is stored in the address store, and the local buffer is released from the high impedance state of allow the external access signal to control the local bus. After the external access signal completes, the address for the address store is supplied to the cache controller for performance of snooping function. If the local store access signal is a read access, then the local buffer is released from its high impedance state after the read access completes.
摘要翻译：用于解决本地处理器与用于访问具有高速度高速缓存的多处理器数据处理系统中的本地存储器的系统资源之间的死锁的设备包括地址存储设备，死锁解决逻辑和死锁检测器。地址存储设备被耦合到本地总线，用于响应于系统总线上的本地存储访问信号来存储地址，并且将地址提供给高速缓存控制器。检测器连接到本地总线和系统总线，以检测死锁状况。死锁分辨率逻辑响应于解决死锁状态的死锁信号产生一系列控制信号。特别地，通过响应于死锁信号来调用本地缓冲器来解决死锁，以禁止外部访问信号控制本地总线，以允许本地存储访问信号来获得对本地总线的控制。如果本地存储访问信号是写访问，则写访问的地址存储在地址存储器中，并且本地缓冲器从高阻抗状态释放以允许外部访问信号来控制本地总线。外部访问信号完成后，将地址存储区的地址提供给缓存控制器，以执行窥探功能。如果本地存储访问信号是读取访问，则在读取访问完成之后，本地缓冲器从其高阻抗状态释放。

33. 发明申请

US20080065796A1 High-Level Bridge From PCIE to Extended USB 失效
标题翻译：从PCIE到扩展USB的高级桥
公开(公告)号：US20080065796A1
公开(公告)日：2008-03-13
申请号：US11926636
申请日：2007-10-29
申请人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
发明人： Charles Lee , David Chow , Abraham Ma , Frank Yu , Ming-Shiang Shen , Horng-Yee Chou
IPC分类号： G06F13/42
CPC分类号： G06F13/28 , G06F12/1416 , G06F21/32 , G06F21/78 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： An extended Universal-Serial Bus (EUSB) bridge to a host computer can have Peripheral Components Interconnect Express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.
摘要翻译：到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连Express（PCIE）协议层，在桥的另一侧可以具有高级桥接转换器模块连接上层。可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。

34. 发明申请

US20060002096A1 System and method for providing a flash memory assembly 有权
标题翻译：用于提供闪存组件的系统和方法
公开(公告)号：US20060002096A1
公开(公告)日：2006-01-05
申请号：US10882539
申请日：2004-06-30
申请人： Kuang-Yu Wang , Charles Lee , Horng-Yee Chou
发明人： Kuang-Yu Wang , Charles Lee , Horng-Yee Chou
IPC分类号： H05K5/03 , H01R13/502
CPC分类号： H05K5/0278 , H01R13/447 , H05K1/181 , H05K1/182 , H05K2201/10189 , H05K2201/10446 , H05K2203/1572
摘要： The present invention relates to a method and system for providing a flash memory assembly. The flash memory assembly includes a connector and a printed circuit board (PCB) coupled to the connector. The center of the PCB is positioned substantially at the center of the connector. An electronic component is coupled to one side of the PCB. In another aspect of the present invention, a second electronic component is coupled to a second side of the PCB. In another aspect of the present invention, the electronic components and the PCB are protected by covers joined using interference fitting or ultrasonic joining. In another aspect of the present invention, a cap protects the connector. The cap can be removably coupled to the connector.
摘要翻译：本发明涉及一种用于提供闪存组件的方法和系统。闪存组件包括连接器和耦合到连接器的印刷电路板（PCB）。 PCB的中心基本上位于连接器的中心。电子部件耦合到PCB的一侧。在本发明的另一方面，第二电子部件耦合到PCB的第二侧。在本发明的另一方面，电子部件和PCB由使用干涉配合或超声波接合连接的盖保护。在本发明的另一方面，帽保护连接器。盖可以可拆卸地联接到连接器。

35. 发明申请

US20050120157A1 USB Smart Switch with Packet Re-Ordering for Interleaving among Multiple Flash-Memory Endpoints Aggregated as a Single Virtual USB Endpoint 失效
标题翻译：具有分组重新排序的USB智能交换机，用于在多个闪存内存端点之间进行交织，聚合为单个虚拟USB端点
公开(公告)号：US20050120157A1
公开(公告)日：2005-06-02
申请号：US10707276
申请日：2003-12-02
申请人： Ben Wei Chen , Horng-Yee Chou , Sun-Teck See
发明人： Ben Wei Chen , Horng-Yee Chou , Sun-Teck See
IPC分类号： G06F13/20 , G06F13/38
CPC分类号： G06F13/385
摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.
摘要翻译：双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。相邻的事务可以通过重新排序重叠。在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

36. 发明申请

US20050059301A1 Dual-Personality Extended-USB Plug and Receptacle with PCI-Express or Serial-AT-Attachment Extensions 失效
标题翻译：具有PCI-Express或串行AT附件扩展功能的双人格扩展USB插头和插座
公开(公告)号：US20050059301A1
公开(公告)日：2005-03-17
申请号：US10708172
申请日：2004-02-12
申请人： Horng-Yee Chou , Ren-Kang Chiou , Ben-Wei Chen
发明人： Horng-Yee Chou , Ren-Kang Chiou , Ben-Wei Chen
IPC分类号： H01R12/00 , H01R13/627 , H01R24/00 , H01R33/00
CPC分类号： H01R13/26 , G06K19/07732 , G06K19/07733 , H01R12/725 , H01R13/658
摘要： An extended Universal-Serial-Bus (USB) connector plug and socket each have a pin substrate with one surface that supports the four metal contact pins for the standard USB interface. An extension of the pin substrate carries another 8 extension metal contact pins that mate when both the connector plug and socket are extended. The extension can be an increased length of the plug's and socket's pin substrate or a reverse side of the substrate. Standard USB connectors do not make contact with the extension metal contacts that are recessed, retracted by a mechanical switch, or on the extension of the socket's pin substrate that a standard USB connector cannot reach. Standard USB sockets do not make contact with the extension metal contacts because the extended connector's extension contacts are recessed, or on the extension of the connector pin substrate that does not fit inside a standard USB socket.
摘要翻译：扩展的通用串行总线（USB）连接器插头和插座每个都具有一个引脚基板，一个表面支持用于标准USB接口的四个金属触点引脚。当两个连接器插头和插座都延伸时，针脚衬底的延伸部分带有另外8个延伸金属接触针。扩展可以是插头和插座的引脚基板或基板的相反侧的增加的长度。标准USB连接器不能与通过机械开关凹入，缩回的扩展金属触点或标准USB连接器无法到达的插座引脚基板延伸部分接触。由于扩展连接器的扩展触点凹进，或者连接器针脚基座的延伸部分不符合标准USB插座，因此标准USB插座不会与延长金属触点接触。

37. 发明申请

US20050138288A1 Dual mode USB and PCI express device 审中-公开
标题翻译：双模式USB和PCI Express设备
公开(公告)号：US20050138288A1
公开(公告)日：2005-06-23
申请号：US10746935
申请日：2003-12-23
申请人： Horng-Yee Chou , Ben Wei Chen , Sun-Teck See
发明人： Horng-Yee Chou , Ben Wei Chen , Sun-Teck See
IPC分类号： G06F12/00 , G06F13/40
CPC分类号： G06F13/409
摘要： A flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.
摘要翻译：用于连接到ExpressCard TM主机的闪存设备包括至少一个闪存模块，用于连接到ExpressCard TM主机的ExpressCard TM连接器，耦合到ExpressCard TM连接器的第一串行接口，以及耦合到所述第一串行接口和所述至少一个闪存模块的控制器。

38. 发明申请

US20050120163A1 Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes 有权
标题翻译：使用类似PCI-Express的数据包和打包数据进行部分页面写入的闪存芯片的串行接口
公开(公告)号：US20050120163A1
公开(公告)日：2005-06-02
申请号：US10708096
申请日：2004-02-09
申请人： Horng-Yee Chou , Ben Wei Chen
发明人： Horng-Yee Chou , Ben Wei Chen
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.
摘要翻译：串行闪存芯片具有到外部控制器的串行总线接口。串行闪速存储器芯片中的闪存块可以由外部控制器通过串行总线发送读取请求数据包到串行闪速存储器芯片读取，串行闪存芯片读取闪存并将数据发送回数据 -payload字段在完成数据包中。写请求数据包中的数据被写入闪速存储器，并且通过串行总线发回消息数据包。串行总线可以是具有双向差分线对的外围组件互连（PCI）Express总线。数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。供应商定义的数据包可以在诸如编程或擦除的操作之后发送闪烁命令，例如复位，擦除或响应。串行引擎和微控制器或状态机位于串行闪存芯片上。

39. 发明申请

US20050120146A1 Single-Chip USB Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage 有权
标题翻译：单芯片USB控制器从用于存储用户的集成闪存读取上电启动代码
公开(公告)号：US20050120146A1
公开(公告)日：2005-06-02
申请号：US10707277
申请日：2003-12-02
申请人： Ben Wei Chen , Horng-Yee Chou , Sun-Teck See , Charles Lee
发明人： Ben Wei Chen , Horng-Yee Chou , Sun-Teck See , Charles Lee
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F3/0679 , Y02D10/14
摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.
摘要翻译：通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

40. 发明申请

US20050114587A1 ExpressCard with On-Card Flash Memory with Shared Flash-Control Bus but Separate Ready Lines 审中-公开
标题翻译： ExpressCard带有带共享闪存控制总线的单卡闪存，但分离就绪线路
公开(公告)号：US20050114587A1
公开(公告)日：2005-05-26
申请号：US10707138
申请日：2003-11-22
申请人： Horng-Yee Chou , Sun-Teck See , Tzu-Yih Chu
发明人： Horng-Yee Chou , Sun-Teck See , Tzu-Yih Chu
IPC分类号： G06F12/00 , G06F13/38
CPC分类号： G06F13/385
摘要： An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.
摘要翻译： ExpressCard包含闪存。 ExpressCard具有插入主机的ExpressCard连接器，如个人计算机，数码相机或个人数字助理（PDA）。 ExpressCard上的控制器芯片使用连接器中的一对差分通用串行总线（USB）数据线与USB主机进行通信，也可以使用PCI Express，Firewire或其他协议。 ExpressCard上的一个或多个闪存芯片由控制器芯片中的闪存控制器控制。闪存总线的两个或更多个通道具有共享控制总线，但是分离的就绪线路。单独的就绪线路允许两个通道中的闪存芯片在不同时间完成操作。

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