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31. 发明授权

US07974142B2 Apparatus and method for transmitting/receiving signals at high speed 有权
标题翻译：高速发送/接收信号的装置和方法
公开(公告)号：US07974142B2
公开(公告)日：2011-07-05
申请号：US12068583
申请日：2008-02-08
申请人： Chang-Ho Do , Jae-Il Kim
发明人： Chang-Ho Do , Jae-Il Kim
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.
摘要翻译：半导体存储器件包括：数据传送器，被配置为传送数据; 主驱动器，被配置为响应于控制信号将数据应用于数据传送器; 以及预驱动器，被配置为当数据传送器的电压电平高于逻辑阈值电压时降低数据传送器的电压电平，并且当数据传送器的电压电平为低于启动控制信号之前的逻辑阈值电压。

32. 发明授权

US07880510B2 Semiconductor device for receiving external signal having receiving circuit using internal reference voltage 有权
标题翻译：用于接收具有使用内部参考电压的接收电路的外部信号的半导体器件
公开(公告)号：US07880510B2
公开(公告)日：2011-02-01
申请号：US12766616
申请日：2010-04-23
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： H03K5/22
CPC分类号： H03K5/1252 , H03K5/003 , H03K5/08 , H04L25/085
摘要： A semiconductor device includes a reference voltage generating unit configured to produce a reference voltage by dividing a voltage difference between a positive clock terminal and a negative clock terminal, and a logic determination unit configured to determine a logic level of an external signal based on the reference voltage.
摘要翻译：一种半导体器件，包括：参考电压生成单元，被配置为通过分压正时钟端子和负时钟端子之间的电压差来产生参考电压;以及逻辑判定单元，被配置为基于所述参考值来确定外部信号的逻辑电平电压。

33. 发明授权

US07839709B2 Semiconductor memory device having I/O unit 失效
标题翻译：具有I / O单元的半导体存储器件
公开(公告)号：US07839709B2
公开(公告)日：2010-11-23
申请号：US12005919
申请日：2007-12-28
申请人： Jae-Il Kim , Chang-Ho Do
发明人： Jae-Il Kim , Chang-Ho Do
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C29/12 , G11C29/1201
摘要： A semiconductor memory device is capable of reducing a test time upon the same condition of the actual operation thereof. The semiconductor memory device includes an output data select unit and a data output unit. The output data select unit selectively outputs valid data, which are loaded on a plurality of global lines, in response to an output control signal activated after a delay time corresponding to an additive latency from entry of a read operation in a test mode. The data output unit aligns data outputted from the output data select unit and outputs the aligned data through data pads.
摘要翻译：半导体存储器件能够在实际操作的相同条件下减少测试时间。半导体存储器件包括输出数据选择单元和数据输出单元。输出数据选择单元响应于在对应于在测试模式中的读取操作的输入的附加等待时间的延迟时间之后激活的输出控制信号，选择性地输出加载在多条全局线路上的有效数据。数据输出单元对准从输出数据选择单元输出的数据，并通过数据垫输出对准的数据。

34. 发明授权

US07764110B2 Internal voltage generating circuit of semiconductor device 失效
标题翻译：半导体器件的内部电压发生电路
公开(公告)号：US07764110B2
公开(公告)日：2010-07-27
申请号：US12164163
申请日：2008-06-30
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock.
摘要翻译：半导体器件的内部电压产生电路包括：第一电压驱动器，其被配置为在内部电压端子的电平低于目标电平的期间内上拉内部电压端子;以及第二电压驱动器，在每个周期内的预定时间内对应于外部时钟的频率的内部电压端子。

35. 发明授权

US07636272B2 Multi-port memory device 有权
公开(公告)号：US07636272B2
公开(公告)日：2009-12-22
申请号：US12288879
申请日：2008-10-24
申请人： Jae-Il Kim , Chang-Ho Do
发明人： Jae-Il Kim , Chang-Ho Do
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C7/1075 , G11C7/1027 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/12 , G11C8/16 , G11C11/4076 , G11C11/4087 , G11C11/4096 , G11C2207/107 , G11C2207/108
摘要： A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

36. 发明申请

US20090313513A1 APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于测试半导体存储器件的装置和方法
公开(公告)号：US20090313513A1
公开(公告)日：2009-12-17
申请号：US12546600
申请日：2009-08-24
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G11C29/10 , G06F11/26
CPC分类号： G11C29/12 , G11C11/401 , G11C29/12005 , G11C2029/1204
摘要： A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
摘要翻译：用于执行可靠性测试的半导体存储器件包括写入驱动块，用于在测试模式中产生预定的测试电压，并且在正常模式下的数据访问操作期间将从外部电路输入的数据传送到本地I / O线对耦合到写入驱动块的本地I / O线对，用于在测试模式中接收预定测试电压;以及单元阵列，其具有分别具有第一和第二位线的多个单位单元和多个位线对，以及耦合到至少一个单元电池，用于从每个本地I / O线对接收预定的测试电压，从而在测试模式下检查可靠性测试的结果。

37. 发明授权

US07594148B2 Apparatus and method for testing semiconductor memory device 有权
标题翻译：半导体存储器件测试装置及方法
公开(公告)号：US07594148B2
公开(公告)日：2009-09-22
申请号：US11024376
申请日：2004-12-27
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/12 , G11C11/401 , G11C29/12005 , G11C2029/1204
摘要： A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode.
摘要翻译：用于执行可靠性测试的半导体存储器件包括写入驱动块，用于在测试模式中产生预定的测试电压，并且在正常模式下的数据访问操作期间将从外部电路输入的数据传送到本地I / O线对耦合到写入驱动块的本地I / O线对，用于在测试模式中接收预定测试电压;以及单元阵列，其具有分别具有第一和第二位线的多个单位单元和多个位线对，以及耦合到至少一个单元电池，用于从每个本地I / O线对接收预定的测试电压，从而在测试模式下检查可靠性测试的结果。

38. 发明授权

US07505297B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07505297B2
公开(公告)日：2009-03-17
申请号：US11480197
申请日：2006-06-29
申请人： Jae-Hyuk Im , Chang-Ho Do
发明人： Jae-Hyuk Im , Chang-Ho Do
IPC分类号： G11C5/06
CPC分类号： G11C5/025 , G11C5/063 , G11C7/065 , G11C11/4074 , G11C11/4091 , G11C2207/065
摘要： Provided are semiconductor design technologies, especially a bit line sense amplifier array of a semiconductor memory device. The semiconductor memory device includes a plurality of unit bit line sense amplifiers, a pull-up power line which is a power line of the plurality of unit bit line sense amplifiers, a single normal driver prepared on one side of the pull-up power line, and a plurality of over drivers arranged at regular intervals and partially connected to the pull-up power line.
摘要翻译：提供半导体设计技术，特别是半导体存储器件的位线读出放大器阵列。半导体存储器件包括多个单位位线读出放大器，作为多个单位位线读出放大器的电源线的上拉电源线，在上拉电源线一侧准备的单个正常驱动器以及以规则间隔布置并部分地连接到上拉电力线的多个过驱动器。

39. 发明申请

US20090059689A1 Apparatus and method for transmitting/receiving signals at high speed 有权
标题翻译：高速发送/接收信号的装置和方法
公开(公告)号：US20090059689A1
公开(公告)日：2009-03-05
申请号：US12068583
申请日：2008-02-08
申请人： Chang-Ho Do , Jae-Il Kim
发明人： Chang-Ho Do , Jae-Il Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1069
摘要： A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal.
摘要翻译：半导体存储器件包括：数据传送器，被配置为传送数据; 主驱动器，被配置为响应于控制信号将数据应用于数据传送器; 以及预驱动器，被配置为当数据传送器的电压电平高于逻辑阈值电压时降低数据传送器的电压电平，并且当数据传送器的电压电平为低于启动控制信号之前的逻辑门限电压。

40. 发明申请

US20090010078A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090010078A1
公开(公告)日：2009-01-08
申请号：US12003684
申请日：2007-12-31
申请人： Chang-Ho Do
发明人： Chang-Ho Do
IPC分类号： G11C5/14 , G11C17/18 , G11C29/00
CPC分类号： G11C29/12 , G11C5/147 , G11C29/12005 , G11C29/1201
摘要： A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged.
摘要翻译：半导体存储器件包括：输入焊盘组，被配置为接收外部输入信号和参考电压; 输入缓冲器组，被配置为通过将输入信号与参考电压进行比较来检测并将输入信号发送到半导体存储器件的内部电路; 以及参考电压生成电路，被配置为产生参考电压以将参考电压提供给在测试操作期间设置的输入焊盘组和输入缓冲器，在半导体存储器件被封装之后，基准电压产生电路被去激活。

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