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31. 发明授权

US09082954B2 PCRAM with current flowing laterally relative to axis defined by electrodes 有权
标题翻译： PCRAM，其电流相对于由电极限定的轴线横向流动
公开(公告)号：US09082954B2
公开(公告)日：2015-07-14
申请号：US13210020
申请日：2011-08-15
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L45/06 , H01L45/1246 , H01L45/144 , H01L45/16
摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.
摘要翻译：改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。在另一示例中，相变结构围绕电介质结构。几种变化改善了相变结构和电极之间的接触。

32. 发明申请

US20100019221A1 FULLY SELF-ALIGNED PORE-TYPE MEMORY CELL HAVING DIODE ACCESS DEVICE 有权
标题翻译：具有二极管访问器件的完全自对准的存储单元
公开(公告)号：US20100019221A1
公开(公告)日：2010-01-28
申请号：US12177533
申请日：2008-07-22
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , Y10S438/90
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

33. 发明授权

US07642125B2 Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing 有权
标题翻译：具有自对准，自会聚底电极的通孔阵列中的相变存储单元及其制造方法
公开(公告)号：US07642125B2
公开(公告)日：2010-01-05
申请号：US11855979
申请日：2007-09-14
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/122 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。存储元件和底部电极是自对准的。

34. 发明申请

US20090072215A1 PHASE CHANGE MEMORY CELL IN VIA ARRAY WITH SELF-ALIGNED, SELF-CONVERGED BOTTOM ELECTRODE AND METHOD FOR MANUFACTURING 有权
标题翻译：通过具有自对准，自适应底层电极的阵列相位改变记忆单元及其制造方法
公开(公告)号：US20090072215A1
公开(公告)日：2009-03-19
申请号：US11855979
申请日：2007-09-14
申请人： Hsiang Lan Lung , Chung Hon Lam
发明人： Hsiang Lan Lung , Chung Hon Lam
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L45/06 , H01L45/122 , H01L45/1253 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.
摘要翻译：通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。存储元件和底部电极是自对准的。

35. 发明申请

US20090027950A1 Block Erase for Phase Change Memory 失效
标题翻译：块擦除相变存储器
公开(公告)号：US20090027950A1
公开(公告)日：2009-01-29
申请号：US11828717
申请日：2007-07-26
申请人： Chung Hon Lam , Hsiang-Lan Lung
发明人： Chung Hon Lam , Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C13/0097 , G11C2013/009 , G11C2213/74
摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.
摘要翻译：本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为至少第二状态。将单元转换到至少第二状态比将单元转换到第一状态更快。至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

36. 发明申请

US20090261313A1 MEMORY CELL HAVING A BURIED PHASE CHANGE REGION AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有相位变化区域的存储单元及其制造方法
公开(公告)号：US20090261313A1
公开(公告)日：2009-10-22
申请号：US12107573
申请日：2008-04-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro Gabriel Schrott
发明人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro Gabriel Schrott
IPC分类号： H01L45/00
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1666
摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
摘要翻译：描述存储单元以及制造方法。本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。电介质围绕底部电极并具有顶部表面。存储元件覆盖在底部电极上，并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部的宽度基本上等于柱的宽度部分底部电极。顶部电极位于存储元件上。

37. 发明授权

US07932506B2 Fully self-aligned pore-type memory cell having diode access device 有权
标题翻译：具有二极管接入装置的全自对准孔型存储单元
公开(公告)号：US07932506B2
公开(公告)日：2011-04-26
申请号：US12177533
申请日：2008-07-22
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1683 , Y10S438/90
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of memory cells. Each memory cell in the plurality of memory cells comprises a diode comprising doped semiconductor material and a dielectric spacer on the diode and defining an opening, the dielectric spacer having sides self-aligned with sides of the diode. Each memory cell further comprises a memory element on the dielectric spacer and including a portion within the opening contacting a top surface of the diode.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的每个存储器单元包括二极管，其包括掺杂半导体材料和二极管上的电介质间隔物，并且限定开口，所述电介质间隔物具有与二极管的侧面自对准的侧面。每个存储单元还包括介质间隔物上的存储元件，并且包括开口内接触二极管顶表面的部分。

38. 发明授权

US07791057B2 Memory cell having a buried phase change region and method for fabricating the same 有权
标题翻译：具有埋置相变区的存储单元及其制造方法
公开(公告)号：US07791057B2
公开(公告)日：2010-09-07
申请号：US12107573
申请日：2008-04-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
发明人： Hsiang-Lan Lung , Chung Hon Lam , Min Yang , Alejandro G. Schrott
IPC分类号： H01L29/02
CPC分类号： H01L45/143 , G11C11/5678 , G11C13/0004 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/144 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1666
摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.
摘要翻译：描述存储单元以及制造方法。本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。电介质围绕底部电极并具有顶部表面。存储元件覆盖在底部电极上并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部具有基本上等于柱的宽度的宽度部分底部电极。顶部电极位于存储元件上。

39. 发明申请

US20120075925A1 PCRAM With Current Flowing Laterally Relative to Axis Defined By Electrodes 有权
标题翻译： PCRAM与当前电流相对于由电极定义的轴流动
公开(公告)号：US20120075925A1
公开(公告)日：2012-03-29
申请号：US13210020
申请日：2011-08-15
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00 , H01L47/00
CPC分类号： H01L45/06 , H01L45/1246 , H01L45/144 , H01L45/16
摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.
摘要翻译：改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。在另一示例中，相变结构围绕电介质结构。几种变化改善了相变结构和电极之间的接触。

40. 发明授权

US07978509B2 Phase change memory with dual word lines and source lines and method of operating same 有权
标题翻译：具有双字线和源极线的相变存储器及其操作方法
公开(公告)号：US07978509B2
公开(公告)日：2011-07-12
申请号：US12759479
申请日：2010-04-13
申请人： Hsiang-Lan Lung , Chung Hon Lam
发明人： Hsiang-Lan Lung , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C8/08 , G11C8/14 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/74 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1625 , H01L45/1675
摘要： A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.
摘要翻译：相变存储器件包括存储单元，第一字线导体和第二字线导体，以及分别响应于第一和第二字线导体的第一和第二存取器件。控制电路被布置为仅使用第一字线导体访问存储器单元用于读取操作，以建立从位线到存储器单元到通过第一存取设备到源极线的电流路径，以及访问存储器单元以进行操作使用第一和第二接入设备来复位存储器单元以建立从位线到存储器单元到两条源极线的电流路径。

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