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31. 发明授权

US06399436B1 Method of making an electric conductive strip 有权
标题翻译：制造导电条的方法
公开(公告)号：US06399436B1
公开(公告)日：2002-06-04
申请号：US09664481
申请日：2000-09-18
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L21/76895 , H01L21/743 , H01L27/10885
摘要： A method for manufacturing a conductive strip includes forming a doped dielectric layer along a surface of the barrier, a vertical surface and a lower horizontal surface. Then, an ion-implanted-sensitive resist is formed over the doped dielectric layer. Next step is to implant ions into the ion-implanted-sensitive resist by substantially vertical implantation such that the ion-implanted-sensitive resist over the lower and upper horizontal surfaces is insoluble portions in a developer and the vertical surface is soluble in the developer. Subsequently, the vertical surface is removed by using the developer and then the doped dielectric layer attached on the vertical surface is also removed. Next, a thermal treatment is used to diffuse the dopants in the doped dielectric layer into the lower horizontal surface, and the barrier layer prevent the dopants from diffusing into the upper horizontal surface.
摘要翻译：一种用于制造导电条的方法包括沿屏障的表面，垂直表面和下水平表面形成掺杂介电层。然后，在掺杂电介质层上形成离子注入敏感性抗蚀剂。下一步是通过基本上垂直的注入将离子注入到离子注入敏感的抗蚀剂中，使得下部和上部水平表面上的离子注入的敏感性抗蚀剂是显影剂中的不溶部分，并且垂直表面可溶于显影剂。随后，通过使用显影剂除去垂直表面，然后除去附着在垂直表面上的掺杂介电层。接下来，使用热处理将掺杂介电层中的掺杂剂扩散到下水平表面中，并且阻挡层防止掺杂剂扩散到上水平表面。

32. 发明授权

US06383937B1 Method of fabricating a silicon island 有权
标题翻译：制造硅岛的方法
公开(公告)号：US06383937B1
公开(公告)日：2002-05-07
申请号：US09715475
申请日：2000-11-17
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2100
CPC分类号： H01L21/76264 , H01L21/84
摘要： A method is disclosed for fabricating a semiconductor device structure which include a thin foot charge drain beneath the device on a silicon substrate. The structures retain high speed operation of SOI devices. In various embodiments, the invention includes forming a first diffusion-barrier layer on a semiconductor substrate, patterning the said first diffusion-barrier layer and the said silicon substrate to certain depth to form a trench, forming a second diffusion-barrier layer and patterning the said second diffusion-barrier layer to form a first spacer on the sidewall of the trench. Performing a directional etching to expose a portion of the sidewall of the trench. Introducing dopants into the said exposed sidewall to form a doped regions near the sidewall. Performing an isotropic etching using halogen gas plasma. Since the etch-rate of the doped silicon is higher than the undoped silicon, the doped silicon is easily and rapidly etched first, as the undoped silicon portion is exposed, the etching rate is substantially decreased or stopped forming a thin foot underneath the silicon island.
摘要翻译：公开了一种用于制造半导体器件结构的方法，其包括在硅衬底上的器件下方的薄的脚电荷漏极。这些结构保留了SOI器件的高速运行。在各种实施方案中，本发明包括在半导体衬底上形成第一扩散阻挡层，将所述第一扩散阻挡层和所述硅衬底图案化到一定深度以形成沟槽，形成第二扩散阻挡层并使所述第二扩散阻挡层在沟槽的侧壁上形成第一间隔物。执行定向蚀刻以暴露沟槽侧壁的一部分。将掺杂剂引入所述暴露的侧壁中以在侧壁附近形成掺杂区域。使用卤素气体等离子体进行各向同性蚀刻。由于掺杂硅的蚀刻速率高于未掺杂的硅，所以首先容易且快速地蚀刻掺杂的硅，因为未掺杂的硅部分被暴露，蚀刻速率基本上减小或停止，在硅岛下方形成薄的底脚。

33. 发明授权

US06376885B1 Semiconductor structure with metal silicide and method for fabricated the structure 有权
标题翻译：具有金属硅化物的半导体结构及其制造方法
公开(公告)号：US06376885B1
公开(公告)日：2002-04-23
申请号：US09670210
申请日：2000-09-25
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2972
CPC分类号： H01L29/66515 , H01L21/28061 , H01L21/28123 , H01L29/41775 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method is directed to form a semiconductor device with silicide formed by a metal layer associated with a deposited silicon layer by providing a substrate. A field oxide layer is formed on a substrate to define an active region. A gate structure is formed on the active region, where the gate structure has a gate oxide layer, a gate layer, and a cap layer on the gate layer. The field oxide layer has a height substantially equal to the cap layer. A spacer is formed on a sidewall of the gate structure. The cap layer is removed to expose the gate layer, whereby a trench is formed. A silicon layer is deposited over the substrate. A refractory metal layer is deposited on the silicon layer. A silicide layer is formed by performing a thermal process to trigger a reaction between the silicon layer and the metal layer. The silicide layer is polished by CMP process using the field oxide layer as a polishing stop. As a result, the silicide fills the trench above the gate layer and the cavity between the spacer and the field oxide layer.
摘要翻译：一种方法是通过提供衬底形成具有由与沉积的硅层相关联的金属层形成的硅化物的半导体器件。在衬底上形成场氧化物层以限定有源区。栅极结构形成在有源区上，其中栅极结构在栅极层上具有栅极氧化物层，栅极层和覆盖层。场氧化物层的高度基本上等于盖层。在栅极结构的侧壁上形成间隔物。去除盖层以露出栅极层，从而形成沟槽。在衬底上沉积硅层。难熔金属层沉积在硅层上。通过进行热处理以触发硅层和金属层之间的反应来形成硅化物层。通过使用场氧化物层作为抛光停止的CMP工艺对硅化物层进行抛光。结果，硅化物填充了栅极层上方的沟槽和间隔物和场氧化物层之间的空腔。

34. 发明授权

US06309923B1 Method of forming the capacitor in DRAM 有权
标题翻译：在DRAM中形成电容器的方法
公开(公告)号：US06309923B1
公开(公告)日：2001-10-30
申请号：US09620068
申请日：2000-07-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/3143 , H01L21/31604 , H01L27/10855 , H01L28/55 , H01L28/84
摘要： A method of forming a capacitor with a self-align structure on a substrate, the substrate including a word line and an active region, the method including the steps of forming a first dielectric layer on the active region and the word line with a planar top surface, creating a contact hole in the first dielectric layer with the self-align structure to expose portions of the active region and the word line, forming a conductive layer on the bottom of the contact hole, forming a polysilicon spacer on the sidewall of the contact hole, forming a dielectric spacer on the sidewall of the polysilicon spacer, filling the contact hole with a polysilicon bar, creating three sub-contact holes by etching back the polysilicon spacer and the polysilicon bar with part of the polysilicon spacer and the polysilicon bar remaining on the bottom, forming a hemispherical grain (HSG) layer on the surface of the sub-contact holes, depositing a second dielectric layer on the hemispherical grain, and forming a top electrode on the second dielectric layer.
摘要翻译：一种在衬底上形成具有自对准结构的电容器的方法，所述衬底包括字线和有源区，所述方法包括以下步骤：在所述有源区上形成第一电介质层，并在所述字线上形成平面顶部在第一电介质层中形成具有自对准结构的接触孔，以暴露有源区和字线的部分，在接触孔的底部形成导电层，在接触孔的侧壁上形成多晶硅间隔物接触孔，在多晶硅间隔物的侧壁上形成电介质间隔物，用多晶硅棒填充接触孔，通过用多晶硅间隔物和多晶硅棒的一部分蚀刻多晶硅间隔物和多晶硅棒来产生三个子接触孔残留在底部，在子接触孔的表面上形成半球状晶粒（HSG）层，在半球形晶粒上沉积第二介电层，并形成第二电介质层上的顶部电极。

35. 发明授权

US06297121B1 Fabrication method for capacitors in integrated circuits with a self-aligned contact structure 有权
标题翻译：具有自对准接触结构的集成电路中的电容器的制造方法
公开(公告)号：US06297121B1
公开(公告)日：2001-10-02
申请号：US09638299
申请日：2000-08-16
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L28/84
摘要： A method of forming a capacitor for use in high density DRAM circuits is described. A layer of silicon dioxide over an integrated circuit wafer having devices formed therein. A contact hole, which is larger at the top of the contact hole than at the bottom of the contact hole, is formed in the layer of silicon dioxide. A layer of polysilicon is then formed on the sidewalls and bottom of the contact hole. Silicon dioxide spacers are then formed on the polysilicon formed on the sidewalls of the contact hole so that a center cavity remains in the contact hole. The center cavity is then filled with polysilicon to form a center pillar which makes electrical contact with the polysilicon at the bottom of the contact hole. The silicon dioxide spacers are then etched away. A capacitor dielectric layer of silicon dioxide is then deposited on the substrate thereby covering the polysilicon pillar in the contact hole and the polysilicon on the sidewalls and bottom of the contact hole. A layer of polysilicon is then formed on the second layer of silicon dioxide to form the second capacitor plate. In one embodiment a layer of hemispherical grain, HSG, polysilicon is formed on the polysilicon forming the first capacitor plate to increase the capacitance.
摘要翻译：描述形成用于高密度DRAM电路的电容器的方法。在其上形成有器件的集成电路晶片上的二氧化硅层。在二氧化硅层中形成接触孔顶部比接触孔底部更大的接触孔。然后在接触孔的侧壁和底部上形成多晶硅层。然后在形成在接触孔的侧壁上的多晶硅上形成二氧化硅间隔物，使得中心腔保留在接触孔中。然后用多晶硅填充中心腔以形成与接触孔底部的多晶硅电接触的中心柱。然后将二氧化硅间隔物蚀刻掉。然后在衬底上沉积二氧化硅的电容器电介质层，从而覆盖接触孔中的多晶硅柱和接触孔的侧壁和底部上的多晶硅。然后在第二二氧化硅层上形成多晶硅层以形成第二电容器板。在一个实施例中，在形成第一电容器板的多晶硅上形成半球形晶粒HSG，多晶硅层以增加电容。

36. 发明授权

US6114202A Method of fabricating dynamic random access memory 有权
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US6114202A
公开(公告)日：2000-09-05
申请号：US329110
申请日：1999-06-09
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/10852 , H01L27/10885 , H01L27/10888 , H01L28/84 , H01L28/91
摘要： A method of fabricating a DRAM. A substrate comprising a MOS is provided. A first dielectric layer is formed on the substrate. The first dielectric layer is patterned to form a bit line contact window exposing a source region of the MOS and a node contact window exposing a drain region of the drain region simultaneously. The bit line window and the node contact window are filled with a bit line and a polysilicon plug by the formation of the same polysilicon layer, respectively. A second dielectric layer with an opening exposing the polysilicon plug is formed on the first dielectric layer. The sidewall and bottom surface of the opening are covered by another polysilicon layer. The second dielectric layer is removed to leave a node contact in contact with the polysilicon plug.
摘要翻译：一种制造DRAM的方法。提供了包括MOS的衬底。在基板上形成第一电介质层。图案化第一电介质层以形成暴露MOS的源极区域的位线接触窗口和同时暴露漏极区域的漏极区域的节点接触窗口。位线窗口和节点接触窗口分别通过形成相同的多晶硅层而填充有位线和多晶硅插塞。在第一介电层上形成具有露出多晶硅插塞的开口的第二电介质层。开口的侧壁和底表面被另一个多晶硅层覆盖。去除第二电介质层以留下与多晶硅插塞接触的节点接触。

37. 发明授权

US6092000A Method for maximizing the throughput of a multiple-step workstation in a plant 失效
标题翻译：用于最大化工厂中多步骤工作站的吞吐量的方法
公开(公告)号：US6092000A
公开(公告)日：2000-07-18
申请号：US958968
申请日：1997-10-28
申请人： Chun-Yen Kuo , Yirn-Sheng Pan , Horng-Huei Tseng
发明人： Chun-Yen Kuo , Yirn-Sheng Pan , Horng-Huei Tseng
IPC分类号： G05B19/418 , G06F19/00
CPC分类号： G05B19/41865 , G05B2219/32294 , G05B2219/45031 , Y02P90/20
摘要： A method for maximizing the throughput of a multiple-step workstation in a plant includes forming an interrecipe delay time array having rows of delay times for a plurality of lots L.sub.n with a plurality of recipes R.sub.n caused by a lot L.sub.n-1 with a recipe R.sub.n-1 for n=1 to a, and columns of delay times for a recipe LR.sub.n caused by a plurality of recipes LR.sub.n-1 for n=1 to a. An array of feasible recipe-to-recipe sequences S(n,m) is then formed having rows of feasible recipe-to-recipe sequences for the lot L.sub.n in a plurality of orders O.sub.m for m=1 to a, and columns of feasible recipe-to-recipe sequences for a plurality of lots L.sub.n in the order O.sub.m for m=1 to a. A recipe-to-recipe sequence in an order that is selected to be processed has a value of 1, and all other sequences in that order have a value of 0. Subsequently, a lot-recipe mapping array is formed that maps a recipe to be used for each lot. An objective function and a constraint function are formed, and may be typical linear programming functions. The objective function is solved subject to the constraint function using an integer programming solver to yield solution sets of recipe-to-recipe sequences having a value of 1. Finally, an optimal process of recipe-to-recipe sequences is formed from lots with minimum total delay times for orders O.sub.1 through O.sub.m.
摘要翻译：用于最大化工厂中的多步骤工作站的吞吐量的方法包括形成具有多个批次Ln的具有多个批次Ln的延迟时间行的配对间延迟时间阵列，其具有由具有配方Rn的批次Ln-1引起的多个配方Rn 对于n = 1到a，-1表示由n = 1到a的多个配方LRn-1引起的配方LRn的延迟时间列。然后形成一系列可行的配方到配方序列S（n，m），其具有针对m = 1至a的多个订单量Om中的批次Ln的可行配方到配方序列的行，以及可行的列对于m = 1到a，多个批次Ln的配方到配方序列的顺序为Om。选择要处理的顺序的配方到配方序列的值为1，并且该顺序中的所有其他序列的值为0.随后，形成批次配方映射数组，将配方映射到用于每一批。形成目标函数和约束函数，可以是典型的线性规划函数。目标函数使用整数规划求解器解决约束函数，以产生具有值为1的配方到配方序列的解集。最后，从最小的批次形成配方到配方序列的最佳过程订单O1至Om的总延迟时间。

38. 发明授权

US6090700A Metallization method for forming interconnects in an integrated circuit 失效
标题翻译：用于在集成电路中形成互连的金属化方法
公开(公告)号：US6090700A
公开(公告)日：2000-07-18
申请号：US616257
申请日：1996-03-15
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/7688 , H01L2924/0002
摘要： A metallization method for forming contact studs and via plugs is disclosed. The method includes: patterning first conductive contacts over a substrate; forming a first dielectric layer over the first conductive contacts and the substrate; forming a sacrificial layer on the first dielectric layer; forming openings through portions of the sacrificial layer and the first dielectric layer until the first conductive contacts are exposed; filling the openings with a second conductive layer; etching back the second conductive layer until the surfaces of the second conductive layer in the openings are near the interface of the sacrificial layer and the first dielectric layer; and removing the sacrificial layer. A metallization method for a multi-level conductive system is also disclosed.
摘要翻译：公开了用于形成接触柱和通孔的金属化方法。该方法包括：在衬底上图案化第一导电接触; 在所述第一导电触头和所述基板上形成第一电介质层; 在所述第一介电层上形成牺牲层; 通过所述牺牲层和所述第一介电层的部分形成开口，直到所述第一导电触点暴露; 用第二导电层填充开口; 蚀刻第二导电层直到开口中的第二导电层的表面靠近牺牲层和第一介电层的界面; 并去除牺牲层。还公开了一种用于多层导电系统的金属化方法。

39. 发明授权

US5889673A Manufacturing method and system for dynamic dispatching of integrated circuit wafer lots 失效
标题翻译：集成电路晶片批量动态调度的制造方法和系统
公开(公告)号：US5889673A
公开(公告)日：1999-03-30
申请号：US775057
申请日：1996-12-27
申请人： Yirn-Sheng Pan , Horng-Huei Tseng
发明人： Yirn-Sheng Pan , Horng-Huei Tseng
IPC分类号： G05B19/418 , H03M5/01
CPC分类号： G05B19/41865 , Y02P90/20
摘要： In dynamic dispatching of integrated circuit wafer lots in an integrated circuit fabrication plant, determine the Stage Achievement Rate (SAR) of descendant stages for each candidate stage to be processed by the fabrication plant. With the loading of descendant stages for each candidate stage, determine the Adjusted Loading (AL), where AL=SAR*(Loading of descendant stages for each candidate stage). Determine the Picked Probability (PP) equal to Normalized 1/AL of grouped descendant stages. Determine the Estimated Loading (EL) of descendant stages for each candidate stage. Determine the Estimated Achievement Rate (EAR) of descendant stages for each candidate stage. Next, determine the Estimated Adjusted Loading (EAL) of descendant stages for each candidate stage. Then determine the Total Estimated Adjusted Loading (TEAL) for each candidate stage. Finally, determine the Dynamic Dispatching Order (DDO) of the wafer lots.
摘要翻译：在集成电路制造工厂的集成电路晶片批量的动态调度中，确定由制造工厂处理的每个候选阶段的后代阶段的阶段成就率（SAR）。随着每个候选阶段的后代阶段的加载，确定调整加载（AL），其中AL = SAR *（每个候选阶段的后代阶段的加载）。确定等于分组后代阶段的归一化1 / AL的选择概率（PP）。确定每个候选阶段的后代阶段的估计负载（EL）。确定每个候选阶段后代阶段的估计成就率（EAR）。接下来，确定每个候选阶段的后代阶段的估计调整加载（EAL）。然后确定每个候选阶段的总预计调整负载（TEAL）。最后，确定晶圆批次的动态调度顺序（DDO）。

40. 发明授权

US5888863A Method to fabricate capacitors in memory circuits 失效
标题翻译：在存储器电路中制造电容器的方法
公开(公告)号：US5888863A
公开(公告)日：1999-03-30
申请号：US649979
申请日：1996-05-16
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method is described for forming a dynamic random access memory cell with an increased capacitance capacitor. Semiconductor devices including a capacitor node contact region are formed. A layer of silicon nitride and an insulating layer are deposited over the devices. A contact is opened through the insulating and silicon nitride layers to the capacitor node contact region. A first layer of polysilicon is deposited over the insulating layer and within the contact opening. A layer of silicon oxide is deposited over the first polysilicon layer. The silicon oxide layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a first distance. The first polysilicon layer is patterned so as to leave this layer only in the area of the planned capacitor and extending outward from the contact opening a second distance smaller than the first distance. A second layer of polysilicon is deposited over the silicon oxide layer. The second polysilicon layer is removed except for spacers on the sidewalls of the silicon oxide layer and portions underlying the spacers. The silicon oxide and insulating layers are etched away leaving the first polysilicon layer with a cylindrical shape wherein the second polysilicon layer has both a horizontal and a vertical fin on each of two sides of its structure. A capacitor dielectric layer and a third polysilicon layer are deposited and patterned to complete formation of the DRAM with capacitor.
摘要翻译：描述了一种用于形成具有增加的电容电容器的动态随机存取存储器单元的方法。形成包括电容器节点接触区域的半导体器件。在器件上沉积氮化硅层和绝缘层。通过绝缘和氮化硅层向电容器节点接触区域打开接触。第一层多晶硅沉积在绝缘层上和接触开口内。在第一多晶硅层上沉积一层氧化硅。图案化硅氧化物层，以便仅在计划电容器的区域中留下该层并且从接触开口向外延伸第一距离。第一多晶硅层被图案化以便仅在计划电容器的区域中留下该层，并且从接触开口向外延伸小于第一距离的第二距离。在氧化硅层上沉积第二层多晶硅。去除第二多晶硅层，除了在氧化硅层的侧壁上的间隔物和间隔物下面的部分之外。蚀刻氧化硅和绝缘层，离开第一多晶硅层，其中第二多晶硅层在其结构的两侧的每一侧具有水平和垂直翅片。沉积并图案化电容器电介质层和第三多晶硅层以完成具有电容器的DRAM的形成。

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