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31. 发明申请

US20050274981A1 Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 审中-公开
标题翻译：包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法
公开(公告)号：US20050274981A1
公开(公告)日：2005-12-15
申请号：US11194529
申请日：2005-08-02
申请人： Ho Lee , Moon-Han Park , Hwa-Sung Rhee , Jae-Yoon Yoo , Seung-Hwan Lee
发明人： Ho Lee , Moon-Han Park , Hwa-Sung Rhee , Jae-Yoon Yoo , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/8238 , H01L31/072 , H01L31/117
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/0251
摘要： A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.
摘要翻译：半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

32. 发明申请

US20050009265A1 Method of fabricating MOS transistor using total gate silicidation process 失效
标题翻译：使用全栅极硅化工艺制造MOS晶体管的方法
公开(公告)号：US20050009265A1
公开(公告)日：2005-01-13
申请号：US10806301
申请日：2004-03-22
申请人： Jae-Yoon Yoo , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
发明人： Jae-Yoon Yoo , Hwa-Sung Rhee , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/84
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823814 , H01L21/823835 , H01L29/4975 , H01L29/66545
摘要： There is provided a method of fabricating a MOS transistor using a total gate silicidation process. The method includes forming an insulated gate pattern on a semiconductor substrate. The insulated gate pattern includes a silicon pattern and a sacrificial layer pattern, which are sequentially stacked. Spacers covering sidewalls of the gate pattern are formed, and source/drain regions are formed by injecting impurity ions into the semiconductor substrate using the spacers and the gate pattern as ion injection masks. The silicon pattern is exposed by removing the sacrificial layer pattern on the semiconductor substrate having the source/drain regions. The exposed silicon pattern is fully converted into a gate silicide layer, and concurrently a source/drain silicide layer is selectively formed on the surface of the source/drain regions.
摘要翻译：提供了使用总栅极硅化工艺制造MOS晶体管的方法。该方法包括在半导体衬底上形成绝缘栅极图案。绝缘栅图案包括依次层叠的硅图案和牺牲层图案。形成覆盖栅极图案的侧壁的间隔物，并且通过使用间隔物和栅极图案作为离子注入掩模将杂质离子注入到半导体衬底中来形成源极/漏极区域。通过去除具有源极/漏极区域的半导体衬底上的牺牲层图案来暴露硅图案。暴露的硅图案完全转换为栅极硅化物层，并且同时在源极/漏极区域的表面上选择性地形成源极/漏极硅化物层。

33. 发明授权

US07033895B2 Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process 有权
标题翻译：使用选择性外延生长工艺制造具有升高的源极/漏极结构的MOS晶体管的方法
公开(公告)号：US07033895B2
公开(公告)日：2006-04-25
申请号：US10823420
申请日：2004-04-13
申请人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
发明人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
IPC分类号： H01L21/336
CPC分类号： H01L29/7834 , H01L29/42376 , H01L29/66477 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
摘要翻译：在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是在形成外延层之后形成，从而防止源极/漏极结区域的劣化。此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

34. 发明授权

US07723193B2 Method of forming an at least penta-sided-channel type of FinFET transistor 有权
标题翻译：形成至少五面通道型FinFET晶体管的方法
公开(公告)号：US07723193B2
公开(公告)日：2010-05-25
申请号：US12149329
申请日：2008-04-30
申请人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
发明人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
IPC分类号： H01L21/336
CPC分类号： H01L29/7853 , H01L29/66795
摘要： An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.
摘要翻译：至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

35. 发明授权

US07385247B2 At least penta-sided-channel type of FinFET transistor 有权
标题翻译：至少五面通道型FinFET晶体管
公开(公告)号：US07385247B2
公开(公告)日：2008-06-10
申请号：US10986018
申请日：2004-11-12
申请人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
发明人： Hwa-Sung Rhee , Hyun-Suk Kim , Ueno Tetsuji , Jae-Yoon Yoo , Seung-Hwan Lee , Ho Lee , Moon-han Park
IPC分类号： H01L29/78
CPC分类号： H01L29/7853 , H01L29/66795
摘要： An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator.
摘要翻译：至少五面通道类型的FinFET晶体管可以包括：基极; 形成在所述基座上的半导体本体，所述主体被布置成较长的尺寸，以使源极/漏极区域夹持沟道区域，至少所述沟道横截面与所述长尺寸的横截面具有至少五个平面基础; 主体通道区上的栅极绝缘体; 以及形成在栅极绝缘体上的栅电极。

36. 发明授权

US07368792B2 MOS transistor with elevated source/drain structure 有权
标题翻译：具有升高的源极/漏极结构的MOS晶体管
公开(公告)号：US07368792B2
公开(公告)日：2008-05-06
申请号：US11388868
申请日：2006-03-24
申请人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
发明人： Seung-hwan Lee , Moon-han Park , Hwa-sung Rhee , Ho Lee , Jae-yoon Yoo
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/42376 , H01L29/66477 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
摘要翻译：在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是在形成外延层之后形成，从而防止源极/漏极结区域的劣化。此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

37. 发明授权

US07354835B2 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US07354835B2
公开(公告)日：2008-04-08
申请号：US11157521
申请日：2005-06-21
申请人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
摘要翻译：在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。同时，通过减少所需掩模的数量来简化制造过程。该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域大于第二导电类型MOS晶体管的有源区中的第一深度。在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层凹陷区域。

38. 发明申请

US20050280098A1 Method of fabricating CMOS transistor and CMOS transistor fabricated thereby 有权
标题翻译：制造CMOS晶体管和CMOS晶体管的方法
公开(公告)号：US20050280098A1
公开(公告)日：2005-12-22
申请号：US11157521
申请日：2005-06-21
申请人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
发明人： Dong-suk Shin , Hwa-sung Rhee , Ueno Tetsuji , Ho Lee , Seung-hwan Lee
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/76
CPC分类号： H01L29/66636 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/165 , H01L29/4933 , H01L29/665 , H01L29/66628 , H01L29/7848
摘要： In a method of fabricating a CMOS transistor, and a CMOS transistor fabricated according to the method, the characteristics of first and second conductivity type MOS transistors are both simultaneously improved. At the same time, the fabrication process is simplified by reducing the number of masks required. The method includes amorphizing the active region of only the second conductivity type MOS transistor, and performing selective etching to form a first recessed region of a first depth in the active region of the first conductivity type MOS transistor and a second recessed region of a second depth that is greater than the first depth in the active region of the second conductivity type MOS transistor. Selective epitaxial growth is performed in the first and second recessed regions to form an elevated epitaxial layer that fills the first recessed region and extends to a level that is above the upper surface of the semiconductor substrate and to form a recessed epitaxial layer that fills the second recessed region.
摘要翻译：在制造CMOS晶体管的方法和根据该方法制造的CMOS晶体管的情况下，第一和第二导电型MOS晶体管的特性都同时改善。同时，通过减少所需掩模的数量来简化制造过程。该方法包括仅使第二导电型MOS晶体管的有源区非晶化，并进行选择性蚀刻，以在第一导电类型MOS晶体管的有源区中形成第一深度的第一凹陷区域和第二深度的第二凹陷区域大于第二导电类型MOS晶体管的有源区中的第一深度。在第一和第二凹陷区域中执行选择性外延生长，以形成一个升高的外延层，其填充第一凹陷区域并延伸到半导体衬底的上表面之上的水平面并形成填充第二凹陷区域的凹陷外延层凹陷区域。

39. 发明申请

US20050023646A1 Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device 有权
标题翻译：包括具有低位错缺陷密度的外延层的多层结构以及包含该外延层的半导体器件以及制造该半导体器件的方法
公开(公告)号：US20050023646A1
公开(公告)日：2005-02-03
申请号：US10851336
申请日：2004-05-24
申请人： Ho Lee , Moon-Han Park , Hwa-Sung Rhee , Jae-Yoon Yoo , Seung-Hwan Lee
发明人： Ho Lee , Moon-Han Park , Hwa-Sung Rhee , Jae-Yoon Yoo , Seung-Hwan Lee
IPC分类号： H01L21/20 , H01L21/8238 , H01L31/072 , H01L31/117
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/0251
摘要： A multi-layered structure of a semiconducotr device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.
摘要翻译：半导体器件的多层结构包括衬底和在衬底上具有低位错缺陷密度的异质外延层。异质外延层由主外延层和在外延层中形成的至少一个中间外延层组成。在其界面处，异质外延层，即主外延层的底部，以及基板具有不同的晶格常数。此外，中间外延层具有与与外延层相邻的主外延层的部分的晶格常数不同的晶格常数。中间外延层的厚度也小于主外延层的净厚度，使得中间外延层吸收异质外延层中的应变。因此，可以获得包括相对薄且具有低位错缺陷密度的外延层的多层结构。

40. 发明申请

US20080036006A1 Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
标题翻译：具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US20080036006A1
公开(公告)日：2008-02-14
申请号：US11802281
申请日：2007-05-22
申请人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

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