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31. 发明申请

US20050207252A1 Semiconductor storage device, test method therefor, and test circuit therefor 失效
标题翻译：半导体存储装置及其测试方法及其测试电路
公开(公告)号：US20050207252A1
公开(公告)日：2005-09-22
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G01R31/28 , G01R31/3185 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/08 , G11C29/14 , G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译：当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。

32. 发明授权

US06751144B2 Semiconductor storage and method for testing the same 有权
标题翻译：半导体存储和测试方法
公开(公告)号：US06751144B2
公开(公告)日：2004-06-15
申请号：US10148430
申请日：2002-05-29
申请人： Hiroyuki Takahashi , Hideo Inaba , Takashi Kusakari
发明人： Hiroyuki Takahashi , Hideo Inaba , Takashi Kusakari
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C29/12
摘要： A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).
摘要翻译：具有与DRAM相同的存储单元的半导体存储器，以SRAM规格工作，具有小斩尺寸，低功耗，低制造成本，无偏移的访问延迟以及无存储器单元故障等优点。 ATD电路（3）根据从外部提供的地址（地址）的改变产生添加到地址变化检测信号（ATD）的单触发脉冲。通过组合为地址的每个位产生的单触发脉冲，即使地址包含偏斜，也只产生一个单触发脉冲。通过使用在产生单次脉冲的时间期间由刷新控制电路（4）产生的刷新地址（R_ADD）来刷新存储器单元。在单触发脉冲的下降时，产生锁存控制信号（LC），并将该地址取入锁存器（2），以访问存储单元阵列（6）。

33. 发明授权

US07193917B2 Semiconductor storage device, test method therefor, and test circuit therefor 失效
标题翻译：半导体存储装置及其测试方法及其测试电路
公开(公告)号：US07193917B2
公开(公告)日：2007-03-20
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译：当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。

34. 发明申请

US20070127299A1 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same 失效
标题翻译：内部电压电平控制电路和半导体存储器件以及其控制方法
公开(公告)号：US20070127299A1
公开(公告)日：2007-06-07
申请号：US11700417
申请日：2007-01-31
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C5/14
CPC分类号： G11C11/406 , G11C5/145 , G11C5/147 , G11C8/08 , G11C11/40615 , G11C11/4074 , G11C11/4085 , G11C2211/4068
摘要： There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes .“H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
摘要翻译：提供了具有降低的功耗的电压电平控制电路及其控制方法。当信号“A”处于“L”电平并且从电压电平控制电路的外部输入的信号PL变为“H”电平时，从锁存器（11）输出的锁存信号La变为“H”电平，由此NFET（14,17,24）导通。包括电阻（12,13）和电流镜差分放大器（20,27）的分压电路被置于有效状态，以输出“H”作为控制升压电压Vbt（字线驱动电压）的信号A，作为升压电压Vbt增加并达到参考电压Vref 2，电压V 2变为“H”，由此信号A变为“L”，在信号A变为“L”之后，锁存器（11）通过这时，信号PL为“L”，从闩锁（11）输出的锁存信号La变为“L”，由此NFET（14,7,24）截止，如上所述，NFET（14,7 ，24）在需要时的其他时间段内保持OFF，以便降低功耗。

35. 发明申请

US20060044889A1 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same 有权
标题翻译：内部电压电平控制电路和半导体存储器件以及其控制方法
公开(公告)号：US20060044889A1
公开(公告)日：2006-03-02
申请号：US11202880
申请日：2005-08-12
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C5/145 , G11C5/147 , G11C8/08 , G11C11/40615 , G11C11/4074 , G11C11/4085 , G11C2211/4068
摘要： There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
摘要翻译：提供了具有降低的功耗的电压电平控制电路及其控制方法。当信号“A”处于“L”电平并且从电压电平控制电路的外部输入的信号PL变为“H”电平时，从锁存器（11）输出的锁存信号La变为“H”电平，由此NFET（14,17,24）导通。包括电阻（12,13）和电流镜差分放大器（20,27）的分压电路被置于有效状态，以输出“H”作为控制升压电压Vbt（字线驱动电压）的信号A，作为升压电压Vbt增加并达到参考电压Vref 2，电压V 2变为“H”，由此信号A变为“L”，在信号A变为“L”之后，锁存器（11）通过这时，信号PL为“L”，从闩锁（11）输出的锁存信号La变为“L”，由此NFET（14,7,24）截止，如上所述，NFET（14,7 ，24）在需要时的其他时间段内保持OFF，以便降低功耗。

36. 发明授权

US06879537B2 Semiconductor storage device having a plurality of operation modes 失效
标题翻译：具有多种操作模式的半导体存储装置
公开(公告)号：US06879537B2
公开(公告)日：2005-04-12
申请号：US10492765
申请日：2002-10-16
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C11/403 , G11C7/20 , G11C11/406 , G11C11/407 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C7/00
CPC分类号： G11C11/40615 , G11C7/20 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first and second timer circuits which respectively output a timer output TN of a constant cycle needed for self-refresh and a timing signal TR of a shorter cycle than a self-refresh cycle. A counter circuit counts the output TR from the second timer circuit immediately after the deep stand-by mode has been transitioned to the stand-by mode. If the counted value corresponds to a value as set, then the counter circuit outputs an operation mode switching signal. A selector circuit comprising a multiplexer is switched and controlled by the output from the counter circuit. The selector circuit remains selecting TR until the counted value of the counter circuit corresponds to the set value, and in the subsequent stand-by mode, the selector circuit selects and outputs TN.
摘要翻译：提供一种操作控制电路，用于在具有深度待机模式和待机模式的伪SRAM中缩短从深度备用模式到待机模式的转换时间。从深度待机模式到待机模式的转变开始分别输出自刷新所需的恒定周期的定时器输出TN和比自动刷新短的周期的定时信号TR的第一和第二定时器电路，刷新周期。在深度待机模式已经转换到待机模式之后，计数器电路立即对来自第二定时器电路的输出TR进行计数。如果计数值对应于设定的值，则计数器电路输出操作模式切换信号。包括多路复用器的选择器电路由计数器电路的输出转换和控制。选择器电路保持选择TR，直到计数器电路的计数值对应于设定值，并且在随后的待机模式中，选择器电路选择和输出TN。

37. 发明授权

US06456559B1 Semiconductor integrated circuit 有权
公开(公告)号：US06456559B1
公开(公告)日：2002-09-24
申请号：US09971227
申请日：2001-10-04
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C8/10
摘要： A semiconductor integrated circuit including a logic circuit having an insulated gate field effect transistor (IGFET) (352) with a reduced threshold voltage that may compensate for a reduced voltage supply is provided. The IGFET may receive a signal line (340) at a gate terminal and may provide a controllable impedance path between a signal line (320) and a node (ND). The logic circuit may include a stand-by mode in which the IGFET (352) may receive a potential at a source electrode that may be approximately equal to the potential at a drain electrode. In this way, leakage current may be reduced.

38. 发明授权

US07852704B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07852704B2
公开(公告)日：2010-12-14
申请号：US12232159
申请日：2008-09-11
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C8/00
CPC分类号： G11C5/145 , G11C7/02 , G11C8/08 , G11C11/4074 , G11C11/4085
摘要： A semiconductor storage device according to one aspect of the present invention includes a DRAM cell including one transistor and one capacitor, in which one of a first voltage and a second voltage is applied to a gate of the transistor, the first voltage being a selected voltage, and the second voltage being a non-selected voltage, a voltage difference between the first voltage and the second voltage is larger than a voltage difference between a power supply voltage and a ground voltage, and one of the ground voltage and the power supply voltage which is closer to the non-selected voltage is applied to a back gate of the transistor irrespective of selection or non-selection.
摘要翻译：根据本发明的一个方面的半导体存储装置包括：DRAM单元，包括一个晶体管和一个电容器，其中第一电压和第二电压中的一个施加到晶体管的栅极，第一电压是选定的电压，第二电压为非选择电压时，第一电压与第二电压之间的电压差大于电源电压与接地电压之间的电压差，接地电压和电源电压之一更接近于非选择电压的电压施加到晶体管的背栅极，而与选择或非选择无关。

39. 发明授权

US06392394B1 Step-down circuit for reducing an external supply voltage 有权
标题翻译：用于降低外部电源电压的降压电路
公开(公告)号：US06392394B1
公开(公告)日：2002-05-21
申请号：US09718212
申请日：2000-11-21
申请人： Atsushi Nakagawa , Hiroyuki Takahashi
发明人： Atsushi Nakagawa , Hiroyuki Takahashi
IPC分类号： G05F316
CPC分类号： G05F3/262
摘要： A step-down circuit according to the present invention for reducing external supply voltage to be supplied from the outside to supply it to the internal circuit is provided with a diode circuit for reducing the external supply voltage by desired voltage to output it as the internal supply voltage, a pull-down transistor for pulling down the internal supply voltage to be outputted from the diode circuit when the external supply voltage drops, and a controlling circuit for controlling the operation of the pull-down transistor.
摘要翻译：根据本发明的降压电路，用于减少从外部提供的外部电源电压以将其提供给内部电路，设置有用于通过期望电压减小外部电源电压的二极管电路，以将其作为内部电源输出电压，当外部电源电压下降时，用于下拉从二极管电路输出的内部电源电压的下拉晶体管，以及用于控制下拉晶体管的操作的控制电路。

40. 发明授权

US07397710B2 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same 失效
标题翻译：内部电压电平控制电路和半导体存储器件以及其控制方法
公开(公告)号：US07397710B2
公开(公告)日：2008-07-08
申请号：US11700417
申请日：2007-01-31
申请人： Hiroyuki Takahashi , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Atsushi Nakagawa
IPC分类号： G11C7/00 , G05F1/10
CPC分类号： G11C11/406 , G11C5/145 , G11C5/147 , G11C8/08 , G11C11/40615 , G11C11/4074 , G11C11/4085 , G11C2211/4068
摘要： There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal “A” is in a “L” level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch (11) becomes “H” level, whereby NFETs (14, 17, 24) turn ON. A voltage dividing circuit comprising resistances (12, 13) and current mirror differential amplifiers (20, 27) are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref2, a voltage V2 becomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch (11) is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch (11) becomes “L”, whereby the NFETs (14, 7, 24) turn OFF. As described here, the NFETs (14, 7, 24) is kept OFF in the other time period than when needed, in order to reduce the power consumption.
摘要翻译：提供了具有降低的功耗的电压电平控制电路及其控制方法。当信号“A”处于“L”电平并且从电压电平控制电路的外部输入的信号PL变为“H”电平时，从锁存器（11）输出的锁存信号La变为“H”电平，由此NFET（14,17,24）导通。包括电阻（12,13）和电流镜差分放大器（20,27）的分压电路被置于有效状态，以输出“H”作为控制升压电压Vbt（字线驱动电压）的信号A，作为升压电压Vbt增加并达到参考电压Vref 2，电压V 2变为“H”，由此信号A变为“L”，在信号A变为“L”之后，锁存器（11）通过这时，信号PL为“L”，从闩锁（11）输出的锁存信号La变为“L”，由此NFET（14,7,24）截止，如上所述，NFET（14,7 ，24）在需要时的其他时间段内保持OFF，以便降低功耗。

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