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31. 发明申请

US20090002048A1 Reference voltage generating circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20090002048A1
公开(公告)日：2009-01-01
申请号：US12230489
申请日：2008-08-29
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： H03L5/00
CPC分类号： G05F3/30
摘要： Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
摘要翻译：公开了一种参考电压产生电路，其包括电阻器R0，R0和R3，差分放大器A1和晶体管Q1，Q2和Q3。晶体管Q1和Q2的集电极连接到差分放大器的差分输入端，而R0，R0和R3的一端共同连接到差分放大器A1的输出端。两个电阻R0的另一端共同连接到晶体管Q1和Q2的集电极，而电阻器R1的另一端连接到晶体管Q3的集电极和基极，晶体管Q3的基极连接到晶体管Q1和Q2的基极。晶体管Q1和Q2的发射极尺寸比设定为1：N。导致大致等于晶体管Q1或Q2的集电极电流的值的电流和大于先前电流的正温度系数的电流流过电阻器R1。参考电压产生电路输出与电阻器R1两端产生的电压和晶体管Q3的基极 - 发射极电压VBE3之和的和相对应的电压。

32. 发明授权

US6088252A Semiconductor storage device with an improved arrangement of electrodes and peripheral circuits to improve operational speed and integration 有权
标题翻译：半导体存储器件具有改进的电极和外围电路的布置，以提高操作速度和集成度
公开(公告)号：US6088252A
公开(公告)日：2000-07-11
申请号：US177889
申请日：1998-10-23
申请人： Hiroki Fujisawa , Masayuki Nakamura
发明人： Hiroki Fujisawa , Masayuki Nakamura
IPC分类号： G11C11/401 , G11C5/02 , G11C8/10 , G11C11/407 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C8/10 , G11C5/025
摘要： A semiconductor storage device is provided in which electrodes are provided so as to be arranged in the central portion so as to divide a semiconductor chip into two segments, an address buffer is provided neighboring those electrodes which receive address signals among said electrodes, memory arrays are constituted so as to be divided into at least two groups sandwiching said central portion, an address decoder is provided on a peripheral side of the semiconductor chip opposite to the central portion where the electrodes of the semiconductor chip are formed, and a predecoder for decoding the address signals is arranged on an intermediate portion extending from said central portion to a portion where said address decoder is provided.
摘要翻译：提供一种半导体存储装置，其中设置电极以便将半导体芯片分成两个部分，将这些电极设置在中心部分中，与在这些电极之间接收地址信号的那些电极相邻设置地址缓冲器，存储器阵列是被构造成被分成夹持所述中心部分的至少两个组，地址解码器设置在半导体芯片的与形成半导体芯片的电极的中心部分相对的周边，以及用于对地址信号被布置在从所述中心部分延伸到提供所述地址解码器的部分的中间部分上。

33. 发明申请

US20100312925A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312925A1
公开(公告)日：2010-12-09
申请号：US12801327
申请日：2010-06-03
申请人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
发明人： Fumiyuki Osanai , Toshio Sugano , Atsushi Hiraishi , Shunichi Saito , Masayuki Nakamura , Hiroki Fujisawa
IPC分类号： G06F13/00 , G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1066 , G11C7/1093 , G11C11/4076 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/3011 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes a plurality of data connectors provided along a long side of a module substrate, a plurality of memory chips and a plurality of data register buffers mounted on the module substrate, a data line that connects the data connectors and the data register buffers, and data lines that connect the data register buffers and the memory chips. Each of the data register buffers and a plurality of data connectors and a plurality of memory chips corresponding to the data register buffer are arranged side by side in a direction of a short side of the module substrate. According to the present invention, because each line length of the data lines is considerably shortened, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括沿着模块衬底的长边提供的多个数据连接器，多个存储器芯片和安装在模块衬底上的多个数据寄存器缓冲器，连接数据连接器和数据寄存器缓冲器的数据线以及连接数据寄存器缓冲器和存储器芯片的数据线。每个数据寄存器缓冲器和多个数据连接器以及对应于数据寄存器缓冲器的多个存储器芯片沿着模块基板的短边方向并排布置。根据本发明，由于数据线的每行长度大大缩短，所以可以实现相当高的数据传送速度。

34. 发明申请

US20100312956A1 Load reduced memory module 审中-公开
标题翻译：减少内存模块
公开(公告)号：US20100312956A1
公开(公告)日：2010-12-09
申请号：US12801325
申请日：2010-06-03
申请人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
发明人： Atsushi Hiraishi , Toshio Sugano , Fumiyuki Osanai , Masayuki Nakamura , Hiroki Fujisawa , Shunichi Saito
IPC分类号： G06F12/00 , G06F3/00
CPC分类号： G11C5/04 , G11C7/1045 , G11C7/1057 , G11C7/1084 , H01L2224/48091 , H01L2224/48227 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.
摘要翻译：存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。至少两个存储器芯片被分配给每个数据寄存器缓冲器。每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

35. 发明授权

US07750726B2 Reference voltage generating circuit 有权
标题翻译：基准电压发生电路
公开(公告)号：US07750726B2
公开(公告)日：2010-07-06
申请号：US12230489
申请日：2008-08-29
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： G05F3/30
摘要： A reference voltage generating circuit includes a current generating section, a voltage generating section, a voltage dividing circuit, and a synthesis section. The current generating section generates a first current having a positive temperature coefficient. The voltage generating section generates a voltage having a negative temperature coefficient. The voltage dividing circuit divides the voltage of the negative temperature coefficient, generated by the voltage generating section. The synthesis section generates a voltage which is the sum of a terminal voltage obtained on causing the first current through a resistor and a voltage obtained on dividing the voltage having the negative temperature coefficient by the voltage dividing circuit, and outputs the sum voltage generated as a reference voltage.
摘要翻译：参考电压产生电路包括电流产生部分，电压产生部分，分压电路和合成部分。电流产生部分产生具有正温度系数的第一电流。电压产生部分产生具有负温度系数的电压。分压电路分压由电压产生部产生的负温度系数的电压。合成部分产生电压，该电压是通过使通过电阻器的第一电流获得的端电压与通过分压电路分压具有负温度系数的电压获得的电压之和，并输出产生的和电压参考电压。

36. 发明申请

US20070132506A1 Reference voltage generating circuit 有权
标题翻译：参考电压发生电路
公开(公告)号：US20070132506A1
公开(公告)日：2007-06-14
申请号：US11603121
申请日：2006-11-22
申请人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
发明人： Hiroki Fujisawa , Masayuki Nakamura , Hitoshi Tanaka
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： Disclosed is a reference voltage generating circuit which includes resistors R0, R0 and R3, a differential amplifier A1 and transistors Q1, Q2 and Q3. The collectors of the transistors Q1 and Q2 are connected to differential input terminals of the differential amplifier, while one ends of the R0, R0 and R3 are connected in common to an output of the differential amplifier A1. The other ends of the two resistors R0 are connected in common to the collectors of the transistors Q1 and Q2, while the other end of the resistor R1 is connected to the collector and the base of the transistor Q3, which transistor Q3 has the base connected to the bases of the transistors Q1 and Q2. The emitter size ratio of the transistors Q1 and Q2 is set to 1:N. A current of a value approximately equal to that of the collector current of the transistor Q1 or Q2 and a current with a positive temperature coefficient larger than the first-stated current are caused to flow through the resistor R1. The reference voltage generating circuit outputs a voltage corresponding to the sum of a voltage generated across both ends of the resistor R1 and a base-to-emitter voltage VBE3 of the transistor Q3.
摘要翻译：公开了一种参考电压发生电路，其包括电阻器R 0，R 0和R 3，差分放大器A 1和晶体管Q 1，Q 2和Q 3。晶体管Q 1和Q 2的集电极连接到差分放大器的差分输入端，而R 0，R 0和R 3的一端共同连接到差分放大器A 1的输出端。两个电阻R 0的另一端共同连接到晶体管Q 1和Q 2的集电极，而电阻器R 1的另一端连接到晶体管Q 3的集电极和基极，该晶体管Q 3 Q 3的基极连接到晶体管Q 1和Q 2的基极。晶体管Q 1和Q 2的发射极尺寸比被设定为1：N。导致大致等于晶体管Q 1或Q 2的集电极电流的值的电流和具有大于第一电流的正温度系数的电流流过电阻器R 1。参考电压产生电路输出与电阻器R 1的两端产生的电压和晶体管Q 3的基极 - 发射极电压V BE3 / N之和的和相对应的电压。

37. 发明授权

US09129437B2 Line plotting method 有权
标题翻译：线绘图法
公开(公告)号：US09129437B2
公开(公告)日：2015-09-08
申请号：US12428212
申请日：2009-04-22
申请人： Kouji Nishikawa , Makoto Adachi , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
发明人： Kouji Nishikawa , Makoto Adachi , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： A line plotting method for plotting lines whose coordinates are given on a display screen on which pixels are arranged according to a prescribed rule, the method includes correcting coordinates at the end point of a line on the basis of which the end point is a starting point or an ending point or whether the end point is inside a prescribed frame determining whether a direction from a starting point of a line after correction toward its ending point horizontally or vertically is the same as a direction from a starting point before correction of a line toward its ending point determining whether integer values of the coordinates of starting and ending points after correction are the same when directions from starting points after and before correction of a line toward their ending points are not matched.
摘要翻译：一种线绘制方法，用于绘制在根据规定的规则排列像素的显示屏上给出其坐标的线，该方法包括校正终点处的起点处的线的终点处的坐标或者终点是否在规定的帧内，确定从校正后的线的起点到水平或垂直的终点的方向是否与从线的校正前的起点的方向相同其终点确定校正后的开始点和结束点的坐标的整数值是否相同，当从线路朝向其终点的校正之前和之后的起始点的方向不匹配时。

38. 发明授权

US08462167B2 Memory access control circuit and image processing system 有权
标题翻译：存储器访问控制电路和图像处理系统
公开(公告)号：US08462167B2
公开(公告)日：2013-06-11
申请号：US12608322
申请日：2009-10-29
申请人： Akihiro Kawahara , Makoto Adachi , Kouji Nishikawa , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
发明人： Akihiro Kawahara , Makoto Adachi , Kouji Nishikawa , Masayuki Nakamura , Motonobu Mamiya , Kae Yamashita
IPC分类号： G06T1/60
CPC分类号： G09G5/397 , G09G5/363 , G09G5/393
摘要： A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.
摘要翻译：存储器访问控制电路包括第一内部寄存器，地址发送单元，其将第一内部寄存器的状态设置为第一状态以发送第一地址，并将第一内部寄存器的状态设置为第二状态，以发送第二内部寄存器地址，第二内部寄存器，数据接收单元，其将第二内部寄存器的状态设置为第三状态，以接收对应于第一地址的第一数据，对延迟的第一数据执行数据处理，设置第二内部寄存器的状态内部寄存器到第四状态以接收对应于第二地址的第二数据，并且在延迟给定延迟时间的第二数据之后对第二数据执行数据处理，第一备份单元和第二备份单元。

39. 发明授权

US08394503B2 Resin-metal bonded article and method for producing the same 有权
标题翻译：树脂金属粘结制品及其制造方法
公开(公告)号：US08394503B2
公开(公告)日：2013-03-12
申请号：US12735062
申请日：2008-12-15
申请人： Masumi Kuroyama , Kazuo Kato , Tomonori Ishikawa , Yaeko Sasaki , Setsuko Sato , Masayuki Nakamura , Shuhei Miura
发明人： Masumi Kuroyama , Kazuo Kato , Tomonori Ishikawa , Yaeko Sasaki , Setsuko Sato , Masayuki Nakamura , Shuhei Miura
IPC分类号： B32B15/04 , B32B15/09 , B32B15/20 , B32B18/00 , B32B37/12
CPC分类号： B29C45/14311 , B29K2067/006 , B29K2081/04 , B29K2705/00 , Y10T156/1089 , Y10T428/31533 , Y10T428/31678 , Y10T428/31681 , Y10T428/31786
摘要： Disclosed is a resin-metal bonded article which is improved in adhesion between a copper component and a PPS or PBT resin. Also disclosed is a method for producing such a resin-metal bonded article. The resin-metal bonded article is obtained by bonding the resin component onto the surface of the copper component through a copper component bonding surface where there is copper oxide in the following range: 10%≦Cu2O/(Cu2O+CuO)≦75%. Preferably, this resin-metal bonded article further contains a triazine thiol derivative in the resin-component-side bonding surface of the copper component.
摘要翻译：公开了一种改善了铜成分和PPS或PBT树脂之间的粘合性的树脂 - 金属接合体。还公开了一种用于制造这种树脂 - 金属粘合制品的方法。树脂金属接合体是通过将铜氧化物的铜成分接合面与铜成分的表面接合而得到的，其中，氧化铜的含量为10％以下; Cu 2 O /（Cu 2 O + CuO）％。优选地，该树脂金属粘合体在铜成分的树脂成分侧接合面中还含有三嗪硫醇衍生物。

40. 发明申请

US20090278459A1 INDUCTION COIL, A PLASMA GENERATOR AND A PLASMA GENERATING METHOD 有权
标题翻译：感应线圈，等离子体发生器和等离子体发生方法
公开(公告)号：US20090278459A1
公开(公告)日：2009-11-12
申请号：US12509434
申请日：2009-07-24
申请人： Georgy K. Vinogradov , Vladimir M. Menagarishvili , Tetsuhiko Shimamura , Masayuki Nakamura
发明人： Georgy K. Vinogradov , Vladimir M. Menagarishvili , Tetsuhiko Shimamura , Masayuki Nakamura
IPC分类号： H05H1/24 , H01F27/29
CPC分类号： H05H1/46 , H01J37/321 , H01J37/3211
摘要： The plasma generator of our invention comprises of the induction coil which is symmetric with respect to the reference plane between two terminal ends. Plasma processing gas is supplied to a predetermined space, and high frequency electricity is supplied to the induction coil, thereby the plasma generator generates plasma in the space. The reference plane passes between the two terminal ends and through longitude axis of the induction coil. The plasma generator can generate plasma with high quality of homogeneous.
摘要翻译：本发明的等离子体发生器包括感应线圈，其相对于两个终端之间的参考平面对称。将等离子体处理气体供给到规定的空间，向感应线圈供给高频电力，等离子体发生器在该空间中产生等离子体。参考平面通过两个终端之间并通过感应线圈的经度轴。等离子体发生器可以产生质量均匀的等离子体。

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