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31. 发明申请

US20080263319A1 UNIVERSAL DIGITAL BLOCK WITH INTEGRATED ARITHMETIC LOGIC UNIT 审中-公开
标题翻译：通用数字块与集成算术逻辑单元
公开(公告)号：US20080263319A1
公开(公告)日：2008-10-23
申请号：US11963661
申请日：2007-12-21
申请人： Warren Snyder , Bert Sullam
发明人： Warren Snyder , Bert Sullam
IPC分类号： G06F13/14 , G06F9/02
CPC分类号： H03K19/177
摘要： An array of universal digital blocks include programmable logic device sections that have uncommitted user programmable logic functions and structural datapath sections that include dedicated and highly configurable arithmetic operators. A routing channel matrix programmably connects to different programmable logic device sections and datapath sections in the different universal digital blocks.
摘要翻译：一组通用数字模块包括具有未提交的用户可编程逻辑功能的可编程逻辑器件部分和包括专用和高度可配置的算术运算符的结构数据通路部分。路由信道矩阵可编程地连接到不同通用数字块中的不同可编程逻辑器件部分和数据路径部分。

32. 发明申请

US20080258760A1 SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING 有权
标题翻译：系统级别与可编程开关互连
公开(公告)号：US20080258760A1
公开(公告)日：2008-10-23
申请号：US11965677
申请日：2007-12-27
申请人： Bert Sullam , Warren Snyder , Haneef Mohammed
发明人： Bert Sullam , Warren Snyder , Haneef Mohammed
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17744 , H03K19/173 , H03K19/177 , H03K19/17704 , H03K19/1776
摘要： Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.
摘要翻译：不同的功能元件都位于相同的集成电路中，其中至少一个功能元件包括微控制器。集成电路中的配置寄存器或配置存储器存储由微控制器加载的配置值。连接器配置为将集成电路连接到外部信号。位于集成电路中的系统级互连可根据加载到配置寄存器中的配置值可编程地将不同功能元件和不同连接器连接在一起。

33. 发明授权

US07023257B1 Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks 有权
标题翻译：用于同步和复位提供给多个可编程模拟块的时钟信号的架构
公开(公告)号：US07023257B1
公开(公告)日：2006-04-04
申请号：US09969313
申请日：2001-10-01
申请人： Bert Sullam
发明人： Bert Sullam
IPC分类号： H03K3/00
CPC分类号： G06F1/12
摘要： A circuit for establishing frequency and phase alignment of clock signals across a domain of analog blocks coupled in a single integrated circuit. Different analog functions are implemented by selectively and electrically coupling different combinations of analog blocks. The analog blocks may be arrayed in a number of columns. The circuit is coupled to the analog blocks to supply a synchronized clock signal to all of the analog blocks in a combination of blocks, even when the blocks are in different columns. The circuit allows the frequency of the clock signal to be changed dynamically depending on the analog function to be achieved. The circuit also establishes phase alignment when a frequency change occurs.
摘要翻译：用于在单个集成电路中耦合的模拟块的域上建立时钟信号的频率和相位对准的电路。通过有选择地和电耦合模拟块的不同组合来实现不同的模拟功能。模拟块可以排列成多个列。该电路耦合到模拟模块，以便在块的组合中向所有模拟块提供同步的时钟信号，即使当块位于不同的列时。电路允许根据要实现的模拟功能动态地改变时钟信号的频率。当发生频率变化时，电路还建立相位对准。

34. 发明授权

US09564902B2 Dynamically configurable and re-configurable data path 有权
标题翻译：动态配置和可重新配置的数据路径
公开(公告)号：US09564902B2
公开(公告)日：2017-02-07
申请号：US11968145
申请日：2007-12-31
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00 , H03K19/177
CPC分类号： H03K19/177
摘要： An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.
摘要翻译：一种装置包括耦合到一个或多个结构运算元件的配置存储器，该配置存储器存储导致结构运算元件执行各种功能的值。该装置还包括系统控制器，用于使用值动态地加载配置存储器，并且提示结构运算元件根据配置存储器存储的值来执行功能。

35. 发明授权

US08838852B1 Programmable interrupt routing system 有权
标题翻译：可编程中断路由系统
公开(公告)号：US08838852B1
公开(公告)日：2014-09-16
申请号：US13415671
申请日：2012-03-08
申请人： Bert Sullam , Haneef Mohammed
发明人： Bert Sullam , Haneef Mohammed
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A method and apparatus to operate programmable routing logic comprise receiving, from a fixed function block, a first request, responsive to the first request, forwarding the first request to a first resource of one or more controllers, the first resource allocated to the fixed function block. The method and apparatus further comprise receiving, from a programmable function block, a second request, and responsive to the second request, forwarding the second request to a second resource of the one or more controllers, the second resource allocated to the programmable function block.
摘要翻译：一种用于操作可编程路由逻辑的方法和装置包括从固定功能块接收响应于第一请求的第一请求，将第一请求转发给一个或多个控制器的第一资源，分配给固定功能的第一资源块。所述方法和装置还包括从可编程功能块接收第二请求，并且响应于所述第二请求，将所述第二请求转发到所述一个或多个控制器的第二资源，所述第二资源被分配给所述可编程功能块。

36. 发明授权

US08516025B2 Clock driven dynamic datapath chaining 有权
标题翻译：时钟驱动动态数据路径链接
公开(公告)号：US08516025B2
公开(公告)日：2013-08-20
申请号：US12104391
申请日：2008-04-16
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F7/38
CPC分类号： H03K19/17728
摘要： A system includes a plurality of datapaths, each having structural arithmetic elements to perform various arithmetic operations based, at least in part, on configuration data. The system also includes a configuration memory coupled to the datapaths, the configuration memory to provide the configuration data to the datapaths, which causes the datapaths to collaborate when performing the arithmetic operations.
摘要翻译：系统包括多个数据路径，每个数据路径具有至少部分地基于配置数据执行各种算术运算的结构运算元件。该系统还包括耦合到数据路径的配置存储器，配置存储器，用于向数据路径提供配置数据，这导致数据路径在执行算术运算时进行协作。

37. 发明授权

US08112551B2 Addressing scheme to allow flexible mapping of functions in a programmable logic array 有权
标题翻译：寻址方案允许在可编程逻辑阵列中灵活地映射功能
公开(公告)号：US08112551B2
公开(公告)日：2012-02-07
申请号：US12776324
申请日：2010-05-07
申请人： Bert Sullam
发明人： Bert Sullam
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F12/06 , G06F12/109
摘要： A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB.
摘要翻译：可编程处理设备包括UDB线性阵列中的多个通用数字块（UDB）。每个UDB中的每个寄存器与多个存储器地址相关联，其中每个存储器地址来自与不同数字外设功能的不同访问模式宽度相关联的不同存储器地址空间。访问模式宽度的数字外设功能被映射到从UDB线性阵列中的第一UDB开始的一个或多个连续的UDB。根据访问模式宽度，为第一个UDB选择一个关联的内存地址。

38. 发明申请

US20080263334A1 DYNAMICALLY CONFIGURABLE AND RE-CONFIGURABLE DATA PATH 有权
标题翻译：动态配置和可配置的数据路径
公开(公告)号：US20080263334A1
公开(公告)日：2008-10-23
申请号：US11968145
申请日：2007-12-31
申请人： Warren Synder , Bert Sullam
发明人： Warren Synder , Bert Sullam
IPC分类号： G06F9/302
CPC分类号： H03K19/177
摘要： An apparatus includes a configuration memory coupled to one or more structural arithmetic elements, the configuration memory to store values that cause the structural arithmetic elements to perform various functions. The apparatus also includes a system controller to dynamically load the configuration memory with values, and to prompt the structural arithmetic elements to perform functions according to the values stored by the configuration memory.
摘要翻译：一种装置包括耦合到一个或多个结构运算元件的配置存储器，该配置存储器存储导致结构运算元件执行各种功能的值。该装置还包括系统控制器，用于使用值动态地加载配置存储器，并且提示结构运算元件根据配置存储器存储的值来执行功能。

39. 发明申请

US20070180279A1 Independent control of core system blocks for power optimization 有权
标题翻译：核心系统块的独立控制功率优化
公开(公告)号：US20070180279A1
公开(公告)日：2007-08-02
申请号：US11343841
申请日：2006-01-31
申请人： Bert Sullam
发明人： Bert Sullam
IPC分类号： G06F1/00
CPC分类号： G06F1/263
摘要： Power management commands are provided to a power management unit of a processing device, wherein the power management unit coupled to a core system block of the processing device. Sampling of the core system block is performed in response to the power management commands by the power management unit, wherein sampling includes periodically powering the core system block.
摘要翻译：电源管理命令被提供给处理设备的电源管理单元，其中电源管理单元耦合到处理设备的核心系统块。核心系统块的采样响应于电力管理单元的功率管理命令来执行，其中采样包括周期性地为核心系统块供电。

40. 发明授权

US07076420B1 Emulator chip/board architecture and interface 失效
标题翻译：仿真器芯片/板结构和接口
公开(公告)号：US07076420B1
公开(公告)日：2006-07-11
申请号：US09975030
申请日：2001-10-10
申请人： Warren Snyder , Craig Nemecek , Bert Sullam
发明人： Warren Snyder , Craig Nemecek , Bert Sullam
IPC分类号： G06F9/455
CPC分类号： G06F11/3656
摘要： A communication interface for an in-circuit emulation system. The interface uses four pins between a virtual microcontroller (an FPGA emulating a microcontroller) and a real microcontroller under test. The bus is fast enough to allow the two devices to operate in synchronization. I/O reads, interrupt vector information and watchdog information is provided over the bus in a time fast enough to allow execution in lock step. Two data lines are provided, one is bi-directional and one is driven only by the microcontroller. A system clock is provided and the microcontroller supplies its clock signal to the FPGA since the microcontroller can operate at varying clock speeds. The bus is time-dependent so more information can be placed on this reduced-pin count bus. Therefore, instructions and data are distinguished based on the time the information is sent within the sequence. The bus can be used to carry trace information, program the flash memory on the microcontroller, perform test control functions, etc.
摘要翻译：用于在线仿真系统的通信接口。该接口在虚拟微控制器（仿真微控制器的FPGA）和正在测试的真实微控制器之间使用四个引脚。总线足够快以允许两个设备同步运行。 I / O读取，中断向量信息和看门狗信息通过总线提供足够快的时间，以允许在锁定步骤中执行。提供两条数据线，一条是双向的，一条仅由微控制器驱动。提供系统时钟，微控制器将其时钟信号提供给FPGA，因为微控制器可以以不同的时钟速度工作。总线是时间依赖的，所以更多的信息可以放在这个减少针数的总线上。因此，指令和数据是根据序列中发送信息的时间来区分的。总线可用于携带跟踪信息，在微控制器上编程闪存，执行测试控制功能等。

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