专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08656121B2 Facilitating data coherency using in-memory tag bits and tag test instructions 失效
标题翻译：使用内存中标记位和标签测试指令促进数据一致性
公开(公告)号：US08656121B2
公开(公告)日：2014-02-18
申请号：US13109254
申请日：2011-05-17
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译：通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供对原始数据的数据修改的细粒度检测。保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。保护位通过专用指令进行设置和清除。响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。

32. 发明授权

US08645644B2 Facilitating data coherency using in-memory tag bits and tag test instructions 失效
标题翻译：使用内存中标记位和标签测试指令促进数据一致性
公开(公告)号：US08645644B2
公开(公告)日：2014-02-04
申请号：US13451682
申请日：2012-04-20
申请人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Geraint North , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译：提供了一种通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联的方法来对原始数据的数据修改进行细粒度检测。保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。保护位通过专用指令进行设置和清除。响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。

33. 发明授权

US08412888B2 Cache-based speculation of stores following synchronizing operations 失效
标题翻译：同步操作后，存储器中基于缓存的推测
公开(公告)号：US08412888B2
公开(公告)日：2013-04-02
申请号：US12985590
申请日：2011-01-06
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0837 , G06F12/0895
摘要： A store request in enqueued in a store queue of a cache memory of the data processing system. The store request identifies a target memory block by a target address and specifies store data. While the store request and a barrier request older than the store request are enqueued in the store queue, a read-claim machine of the cache memory is dispatched to acquire coherence ownership of target memory block of the store request. After coherence ownership of the target memory block is acquired and the barrier request has been retired from the store queue, a cache array of the cache memory is updated with the store data.
摘要翻译：在数据处理系统的高速缓冲存储器的存储队列中排队的存储请求。存储请求通过目标地址识别目标存储器块并指定存储数据。当存储请求和存储请求之前的屏障请求在存储队列中排队时，调度高速缓冲存储器的读取机器以获取存储请求的目标存储器块的一致性所有权。在获取目标存储器块的一致性所有权并且屏障请求已经从存储队列中退出之后，用存储数据更新高速缓冲存储器的高速缓存阵列。

34. 发明授权

US08370595B2 Aggregate data processing system having multiple overlapping synthetic computers 有权
标题翻译：具有多个重叠合成计算机的综合数据处理系统
公开(公告)号：US08370595B2
公开(公告)日：2013-02-05
申请号：US12643800
申请日：2009-12-21
申请人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Charles F. Marino , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译：第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元，第四和第五系统内存池。第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问第四和第五处理单元。第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。

35. 发明申请

US20120203973A1 SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS 审中-公开
标题翻译：选择性高速缓存行驶路线
公开(公告)号：US20120203973A1
公开(公告)日：2012-08-09
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

36. 发明授权

US08140771B2 Partial cache line storage-modifying operation based upon a hint 有权
标题翻译：基于提示的部分缓存行存储修改操作
公开(公告)号：US08140771B2
公开(公告)日：2012-03-20
申请号：US12024424
申请日：2008-02-01
申请人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Ravi K. Arimilli , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/04 , G06F9/312
CPC分类号： G06F12/0822
摘要： In at least one embodiment, a method of data processing in a data processing system having a memory hierarchy includes a processor core executing a storage-modifying memory access instruction to determine a memory address. The processor core transmits to a cache memory within the memory hierarchy a storage-modifying memory access request including the memory address, an indication of a memory access type, and, if present, a partial cache line hint signaling access to less than all granules of a target cache line of data associated with the memory address. In response to the storage-modifying memory access request, the cache memory performs a storage-modifying access to all granules of the target cache line of data if the partial cache line hint is not present and performs a storage-modifying access to less than all granules of the target cache line of data if the partial cache line hint is present.
摘要翻译：在至少一个实施例中，具有存储器层次的数据处理系统中的数据处理方法包括执行存储修改存储器访问指令以确定存储器地址的处理器核心。处理器核心向存储器层级内的高速缓冲存储器传送存储修改存储器访问请求，该存储修改存储器访问请求包括存储器地址，存储器访问类型的指示，以及如果存在的话，部分高速缓存行提示信令访问少于所有颗粒的与存储器地址相关联的数据的目标高速缓存行。响应于存储修改存储器访问请求，如果不存在部分高速缓存行提示，则高速缓存存储器对目标高速缓存行数据行的所有颗粒进行存储修改访问，并执行对小于全部的存储修改访问如果存在部分高速缓存线提示，则目标高速缓存行数据的颗粒。

37. 发明申请

US20110161587A1 PROACTIVE PREFETCH THROTTLING 有权
标题翻译：主动推荐曲线
公开(公告)号：US20110161587A1
公开(公告)日：2011-06-30
申请号：US12649548
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0815
摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统中的多个处理器核心接收多个数据预取请求，其中多个预取负载请求包括由多处理器中的特定处理器核发出的数据预取请求核心。响应于接收到数据预取请求，存储器控制器提供指示多余数据预取请求的一致性响应。响应于一致性响应，特定处理器核心降低了数据预取请求的发布速率。

38. 发明授权

US07716428B2 Data processing system, cache system and method for reducing imprecise invalid coherency states 失效
标题翻译：数据处理系统，缓存系统和减少不精确无效一致性状态的方法
公开(公告)号：US07716428B2
公开(公告)日：2010-05-11
申请号：US11364774
申请日：2006-02-28
申请人： Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态，存储位置不包含有效数据。响应于窥探数据无效状态更新请求，第一缓存存储器将相关性状态字段从第一数据无效一致性状态更新为指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，并且与地址标签相关联的存储器块可能被缓存在第一个相干域内。

39. 发明授权

US07689771B2 Coherency management of castouts 有权
标题翻译： castouts的一致性管理
公开(公告)号：US07689771B2
公开(公告)日：2010-03-30
申请号：US11532981
申请日：2006-09-19
申请人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
发明人： James S. Fields, Jr. , Guy L. Guthrie , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815
摘要： According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory. The castout request includes an indication of a shared ownership coherency state. In response to the castout request, the cache line is placed in the lower level cache memory in a coherency state determined in accordance with the castout request.
摘要翻译：根据一个实施例，一种数据处理系统中的一致性管理方法包括：将高速缓存行以独占所有权一致性状态保存在上级高速缓冲存储器中，之后从高级缓存存储器中移除高速缓存行，从高级缓存存储器到高级缓存的高速缓存行。丢弃请求包括共享所有权一致性状态的指示。响应于抛出请求，高速缓存行以根据转储请求确定的一致性状态被放置在较低级高速缓冲存储器中。

40. 发明授权

US07523268B2 Reducing number of rejected snoop requests by extending time to respond to snoop request 有权
标题翻译：通过延长响应窥探请求的时间来减少被拒绝的窥探请求数
公开(公告)号：US07523268B2
公开(公告)日：2009-04-21
申请号：US12114790
申请日：2008-05-04
申请人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
发明人： Guy L. Guthrie , Hugh Shen , William J. Starke , Derek E. Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.
摘要翻译：用于减少拒绝的窥探请求数量的缓存，系统和方法。如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式