专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US09092645B2 Efficient multiplication, exponentiation and modular reduction implementations 有权
标题翻译：有效的乘法，乘法和模块化削减实现
公开(公告)号：US09092645B2
公开(公告)日：2015-07-28
申请号：US13994782
申请日：2011-12-05
申请人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： H04L29/00 , G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

32. 发明申请

US20150082047A1 EFFICIENT MULTIPLICATION, EXPONENTIATION AND MODULAR REDUCTION IMPLEMENTATIONS 有权
标题翻译：有效的实施，授权和模块化的减少实施
公开(公告)号：US20150082047A1
公开(公告)日：2015-03-19
申请号：US13994782
申请日：2011-12-05
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
发明人： Erdinc Ozturk , Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Deniz Karakoyunlu , Martin G. Dixon , Kahraman D. Akdemir
IPC分类号： G06F21/71 , H04L9/30
CPC分类号： G06F21/71 , G06F7/723 , H04L9/3006 , H04L2209/12
摘要： In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment et and a number t of k-bit segments ei in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment ei, wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R=ge mod m based on, at least in part, at least one respective intermediate modular exponentiation result.
摘要翻译：在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，并且k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

33. 发明申请

US20130290285A1 DIGEST GENERATION 有权
标题翻译：最终生成
公开(公告)号：US20130290285A1
公开(公告)日：2013-10-31
申请号：US13995236
申请日：2011-11-01
申请人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
发明人： Vinodh Gopal , James D. Guilford , Schuyler Eldridge , Gilbert M. Wolrich , Erdinc Ozturk , Wajdi K. Feghali
IPC分类号： G06F17/30
CPC分类号： G06F17/30303 , G06F17/30306 , G06F17/3033
摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.
摘要翻译：在一个实施例中，电路可以生成待组合的摘要以产生散列值。摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

34. 发明授权

US08073892B2 Cryptographic system, method and multiplier 有权
标题翻译：加密系统，方法和乘数
公开(公告)号：US08073892B2
公开(公告)日：2011-12-06
申请号：US11323994
申请日：2005-12-30
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel R. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F7/52
CPC分类号： G06F7/5275
摘要： In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.
摘要翻译：通常，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的组具有访问第一操作数和第二操作数以乘以具有多个段的第一操作数和第二操作数具有多个段的操作数。所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的相应一个，直到所述第二操作数已被提供给第一个操作数的每个段。该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器中的不同乘法器的输出。乘法器还包括耦合到逻辑的累加器。

35. 发明授权

US07900022B2 Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction 有权
标题翻译：可编程处理单元，具有输入缓冲器和输出缓冲器，其被配置为基于模式指令与共享存储器逻辑或乘法器专门交换数据
公开(公告)号：US07900022B2
公开(公告)日：2011-03-01
申请号：US11354404
申请日：2006-02-14
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F7/5324 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/383 , G06F21/602 , G06F21/72
摘要： In general, in one aspect, a processing unit includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
摘要翻译：通常，在一个方面，处理单元包括：输入缓冲器，用于存储由处理单元接收的数据;存储器;耦合到输入缓冲器和存储器的算术逻辑单元;输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。

36. 发明申请

US20100332578A1 Method and apparatus for performing efficient side-channel attack resistant reduction 有权
标题翻译：用于执行有效的侧信道抗攻击降低的方法和装置
公开(公告)号：US20100332578A1
公开(公告)日：2010-12-30
申请号：US12459152
申请日：2009-06-26
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
IPC分类号： G06F7/52 , G06F12/08 , G06F7/50 , H04L9/30
CPC分类号： G06F7/72 , G06F12/0802 , G06F12/14 , G06F2207/7261
摘要： A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.
摘要翻译：提供了一种用于执行防止基于高速缓存和基于分支的攻击的模块化降级的时不变方法和装置。模块化还原技术不会增加性能损失，并且具有侧向通道阻抗。通过使用进位位的惰性评估，消除数据相关分支以及对所有存储器引用使用甚至高速缓存访问来提供侧向通道电阻。

37. 发明申请

US20140019694A1 PARALLELL PROCESSING OF A SINGLE DATA BUFFER 审中-公开
标题翻译：单数据缓冲器的并行处理
公开(公告)号：US20140019694A1
公开(公告)日：2014-01-16
申请号：US13631763
申请日：2012-09-28
申请人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
发明人： Sean M. Gulley , Wajdi K. Feghali , Vinodh Gopal , James D. Guilford , Gilbert Wolrich , Kirk S. Yap
IPC分类号： G06F12/00
CPC分类号： G06F5/06 , G06F21/64 , H04L9/0643 , H04L9/3236 , H04L2209/12 , H04L2209/20
摘要： Technologies for executing a serial data processing algorithm on a single variable-length data buffer includes padding data segments of the buffer, streaming the data segments into a data register and executing the serial data processing algorithm on each of the segments in parallel.
摘要翻译：用于在单个可变长度数据缓冲器上执行串行数据处理算法的技术包括缓冲器的填充数据段，将数据段流传输到数据寄存器中，并且并行地对每个段执行串行数据处理算法。

38. 发明授权

US09990201B2 Multiplication instruction for which execution completes without writing a carry flag 有权
公开(公告)号：US09990201B2
公开(公告)日：2018-06-05
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdine Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.

39. 发明授权

US08504807B2 Rotate instructions that complete execution without reading carry flag 有权
公开(公告)号：US08504807B2
公开(公告)日：2013-08-06
申请号：US12655213
申请日：2009-12-26
申请人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
发明人： Vinodh Gopal , James D. Guilford , Gilbert M. Wolrich , Wajdi K. Feghali , Erdinc Ozturk , Martin G. Dixon , Sean P. Mirkes , Bret L. Toll , Maxim Loktyukhin , Mark C. Davis , Alexandre J. Farcy
IPC分类号： G06F9/00
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/30098
摘要： A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

40. 发明授权

US08392494B2 Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction 有权
标题翻译：使用montgomery或barrett还原来执行有效的侧信道攻击抗拒降低的方法和装置
公开(公告)号：US08392494B2
公开(公告)日：2013-03-05
申请号：US12459152
申请日：2009-06-26
申请人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
发明人： Vinodh Gopal , Gilbert M. Wolrich , Wajdi K. Feghali , James D. Guilford , Erdinc Ozturk , Martin G. Dixon
IPC分类号： G06F7/52 , G06F17/30
CPC分类号： G06F7/72 , G06F12/0802 , G06F12/14 , G06F2207/7261
摘要： A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.
摘要翻译：提供了一种用于执行防止基于高速缓存和基于分支的攻击的模块化降级的时不变方法和装置。模块化还原技术不会增加性能损失，并且具有侧向通道阻抗。通过使用进位位的惰性评估，消除数据相关分支以及对所有存储器引用使用甚至高速缓存访问来提供侧向通道电阻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式