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31. 发明授权

US06369736B2 Data converter with vertical resistor meander 有权
标题翻译：数据转换器与垂直电阻器曲折
公开(公告)号：US06369736B2
公开(公告)日：2002-04-09
申请号：US09740302
申请日：2000-12-18
申请人： Hiep V. Tran , Shivaling S. Mahant-Shetti
发明人： Hiep V. Tran , Shivaling S. Mahant-Shetti
IPC分类号： H03M166
CPC分类号： H03M1/685 , H01L28/20 , H03M1/765
摘要： A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output. Lastly, for each of a majority of the plurality of word lines the word line is coupled to at least one gate of a switching transistor located on a first side of the word line and to at least one gate of a switching transistor located on a second side of the word line, wherein the second side is opposite the first side.
摘要翻译：一种数据转换器（20），包括用于接收数字字的输入（I0'-I3'）和用于响应于数字字提供模拟电压电平的输出（VOUT2）。数据转换器还包括形成有第一维度的对齐的多个位线（BL0'-BL3'）和多个字线（WL0'-WL4'），其形成为具有与第一尺寸不同的第二尺寸的对准尺寸。此外，数据转换器包括包括多个串联连接的电阻元件（R0'-R14'）的串（12'）。串包括多个电压抽头（T0'-T15'），并且多个串联电阻元件的至少大部分在第一维度上形成对准。数据转换器还包括耦合在多个电压抽头和输出之间的多个开关晶体管（ST0'-ST15'）。最后，对于多数字线中的大多数，字线被耦合到位于字线的第一侧上的开关晶体管的至少一个栅极和位于第二个字线上的开关晶体管的至少一个栅极字线的一侧，其中第二侧与第一侧相对。

32. 发明授权

US6144768A Method of decoding image data 失效
标题翻译：图像数据解码方法
公开(公告)号：US6144768A
公开(公告)日：2000-11-07
申请号：US845533
申请日：1997-04-25
申请人： Shivaling S. Mahant-Shetti , Whoi Yul Kim
发明人： Shivaling S. Mahant-Shetti , Whoi Yul Kim
IPC分类号： H04N7/30 , G06T9/00 , H04N1/41 , G06K9/36
CPC分类号： G06T9/007 , G06T9/005
摘要： An image encoding/decoding system (10) includes an encoder section (12) and a decoder section (14). The encoder section (12) includes an image detector (15), a transform processor (16), a quantizer (18), a zig-zag process memory (20), and a run/variable length encoder (22). The decoder section includes a variable/run length decoder (24), a dequantizer (26), a zig-zag deprocess memory (28), and an inverse transform processor (30). The inverse transform processor (30) within the decoder section (14) uses basis functions (58) based on a discrete articulated trapezoid transform for ease of realizability in decoding image data. The discrete articulated trapezoid transform may also be used by the transform processor (16) within the encoder section (12) for the encoding of detected images.
摘要翻译：图像编码/解码系统（10）包括编码器部分（12）和解码器部分（14）。编码器部分（12）包括图像检测器（15），变换处理器（16），量化器（18），之字形处理存储器（20）和运行/可变长度编码器（22）。解码器部分包括可变/游程长度解码器（24），去量化器（26），之字形去处理存储器（28）和逆变换处理器（30）。在解码器部分（14）中的逆变换处理器（30）使用基于功能（58）的基础函数（58），以便易于解码图像数据的可实现性。离散铰接梯形变换也可以由编码器部分（12）内的变换处理器（16）用于检测图像的编码。

33. 发明授权

US5926039A Active load for an N channel logic network 失效
标题翻译： N通道逻辑网络的有效负载
公开(公告)号：US5926039A
公开(公告)日：1999-07-20
申请号：US820728
申请日：1997-03-19
申请人： Shivaling S. Mahant-Shetti , Kameshwar C. Rao
发明人： Shivaling S. Mahant-Shetti , Kameshwar C. Rao
IPC分类号： H03K19/017 , H03K19/096
CPC分类号： H03K19/0963 , H03K19/01742
摘要： An active load (12) is provided for an N channel logic network (10). The active load (12) includes a P channel device (28) coupled to the output node (14) of the N channel network (10). A clock circuit (16) of the active load (12) determines whether the N channel network (10) is in a steady state or a switching mode. If the N channel network (10) is in a switching mode, an intermediate voltage level, V.sub.bias, is applied at the gate of the P channel device (28) to facilitate fast switching at the output node (14) with low quiescent power consumption and without compromising compact semiconductor layout.
摘要翻译：为N通道逻辑网络（10）提供有效负载（12）。有源负载（12）包括耦合到N信道网络（10）的输出节点（14）的P信道设备（28）。有源负载（12）的时钟电路（16）确定N信道网络（10）是处于稳定状态还是切换模式。如果N沟道网络（10）处于开关模式，则在P沟道器件（28）的栅极处施加中间电压电平Vbias，以便在输出节点（14）处以低静态功耗快速切换并且不会影响紧凑的半导体布局。

34. 发明授权

US5793068A Compact gate array 失效
标题翻译：紧凑型门阵列
公开(公告)号：US5793068A
公开(公告)日：1998-08-11
申请号：US475759
申请日：1995-10-16
申请人： Shivaling S. Mahant-Shetti
发明人： Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L27/118 , H01L27/10
CPC分类号： H01L27/11803
摘要： The gate array (10) has a first doped region (14) in a semiconductor substrate (12) and a plurality of contacts (20-20"', 21-21") arranged in rows and columns to the first doped region (14) organized with contacts of each row offset in a column (25) that is spaced with respect to a columns (28) of adjacent rows at which a contact exists. A plurality of gate conductors (35-42) are arranged to circumnavigate successive contacts (20,21) of adjacent rows on opposite sides in a serpentine patterns, preferably that follow partially circular paths. The contacts (20,21) are substantially circular in cross section, and may be provided with cap (32) on each that may also have a substantially circular cross section. The contacts (20-21) are spaced with a predetermined pitch and the gate conductors (35-42) have a width that defines transistor channels between adjacent contacts. The width of the conductors (35-42) allows the conductors to pass in proximity to the contacts (20-21) with a predetermined spacing. The gate array (10) may have in the substrate a second doped region (15) of an opposite conductivity type from a conductivity type of the first doped region (14). A gate array similar to that constructed above the first doped region is constructed above the second doped region to enable diverse logic circuits to be constructed by selective interconnections among selected contact and gate conductors (50,51).
摘要翻译：栅极阵列（10）在半导体衬底（12）中具有第一掺杂区域（14）和以行和列排列到第一掺杂区域的多个触点（20-20“，21-21”）（14），其以相对于存在触点的相邻行的列（28）间隔开的列（25）中的每行偏移的触点组织。多个栅极导体（35-42）布置成环绕在相对侧上的相邻行的连续接触（20,21），以蛇形图案，优选地遵循部分圆形路径。触头（20,21）的横截面基本上为圆形，并且每个触头（20,21）可以设置有也可具有基本圆形横截面的盖（32）。触点（20-21）以预定间距间隔开，并且栅极导体（35-42）具有限定相邻触点之间的晶体管通道的宽度。导体（35-42）的宽度允许导体以预定间隔通过接触件（20-21）。栅极阵列（10）可以在衬底中具有与第一掺杂区域（14）的导电类型相反的导电类型的第二掺杂区域（15）。在第二掺杂区域之上构造类似于在第一掺杂区域之上构造的门阵列，以使能不同的逻辑电路通过选择的接触和栅极导体（50,51）之间的选择性互连构成。

35. 发明授权

US5217915A Method of making gate array base cell 失效
标题翻译：制造栅极阵列基体的方法
公开(公告)号：US5217915A
公开(公告)日：1993-06-08
申请号：US681822
申请日：1991-04-08
申请人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Mashashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L27/118
CPC分类号： H01L27/11807 , H01L21/8238
摘要： A gate array base cell which can easily be configured as high conductivity transistor device or a low conductivity transistor device comprises a moat region of first conductivity type, typically heavily doped n-type silicon or heavily doped p-type silicon, for example. A channel region of a different conductivity type separates the moat region into at least three portions. An insulating layer, such as silicon dioxide, for example, and a gate are formed above the channel region. The gate may be formed of polysilicon, for example. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.

36. 发明授权

US5068825A Memory cell circuit and operation thereof 失效
标题翻译：存储单元电路及其操作
公开(公告)号：US5068825A
公开(公告)日：1991-11-26
申请号：US546497
申请日：1990-06-29
申请人： Shivaling S. Mahant-Shetti , Mark G. Harward
发明人： Shivaling S. Mahant-Shetti , Mark G. Harward
IPC分类号： G11C11/413 , G11C11/412 , G11C11/418
CPC分类号： G11C11/412
摘要： An improved memory cell 118 is provided utilizing transistor pairs 142, 144 ands 160, 162 as dual purpose transistor pairs for the two modes of operation of the cell. During the first or non-access mode of operation, the transistor pairs operate as switched capacitive elements in order to provide an equivalent resistance between bit line 140 and first node 26 and inverted bit line 158 and second node 130. Control circuit 119 maintains bit lines 140 and inverted bit line 158 high during this non-access mode. During the second or access mode of operation, each transistor pair operates as a respective pass transistor for connecting bit line 140 to first node 126 and inverted bit line 158 to second node 130 so that data may be read from, or written to, the cross-coupled transistors 120 and 122.

37. 发明授权

US4601019A Memory with redundancy 失效
标题翻译：内存冗余
公开(公告)号：US4601019A
公开(公告)日：1986-07-15
申请号：US528209
申请日：1983-08-31
申请人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
发明人： Ashwin H. Shah , James D. Gallia , I-Fay Wang , Shivaling S. Mahant-Shetti
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/808
摘要： A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally received column address and the stored defective-column-address is found, the sense amplifier for the bit position which contains that defective column is disabled, and the output of the redundant column (selected by whichever word line is activated) is multiplexed into the I-O buss. Thus, before the row address signal has even been decoded, the defective column has been disabled and one of the redundant columns has effectively been substituted. This configuration means that it is not necessary to have one redundant column for every bit position, but each redundant column can substitute for a defective column in any bit position, and more than one defective column in a single bit position can each be replaced.
摘要翻译：具有列冗余的字节宽的内存。冗余列可以分别代替半数组中的任何列，而不考虑缺陷列与哪个位的关系。保险丝存储有缺陷列的地址信息，当外部接收的列地址与存储的故障列地址之间的匹配被找到时，包含该缺陷列的位位置的读出放大器被禁止，并且输出冗余列（由哪个字线被激活选择）被复用到IO总线中。因此，在行地址信号甚至被解码之前，有缺陷的列已经被禁用，并且冗余列之一被有效地替代。该配置意味着对于每个位位置不需要具有一个冗余列，但是每个冗余列可以替代任何位位置中的有缺陷的列，并且可以替换单个位位置中的多于一个的有缺陷的列。

38. 发明授权

US06567346B2 Absolute time scale clock 有权
公开(公告)号：US06567346B2
公开(公告)日：2003-05-20
申请号：US09757074
申请日：2001-01-08
申请人： Thomas J. Aton , Shivaling S. Mahant-Shetti
发明人： Thomas J. Aton , Shivaling S. Mahant-Shetti
IPC分类号： G04C1500
CPC分类号： G04F5/16
摘要： An absolute time scale clock includes a radioactive isotope and a computer. The computer includes a processor that determines an indication of the current absolute time and a memory that stores a decay constant of the radioactive isotope, a reference time, and an amount of the isotope at the reference time. A energy supply that provides power to the computer. The absolute time scale clock further includes a detector positioned to respond to emissions from the radioactive isotope. The detector generates an indication of the number of emissions over a time interval that varies with the decay rate of the isotope. The processor is responsive to the indication from the detector, the decay constant, the reference time, and the reference amount to determine the indication of current absolute time.

39. 发明授权

US06529238B1 Method and apparatus for compensation of point noise in CMOS imagers 有权
标题翻译： CMOS成像器中点噪声补偿的方法和装置
公开(公告)号：US06529238B1
公开(公告)日：2003-03-04
申请号：US09145385
申请日：1998-09-01
申请人： Shivaling S. Mahant-Shetti , David A. Martin
发明人： Shivaling S. Mahant-Shetti , David A. Martin
IPC分类号： H04N964
CPC分类号： H04N5/367
摘要： This invention corrects of white spot noise in an imager. If the brightness value of a pixel is greater than the maximum brightness value of eight surrounding pixels, then the compensated output is this maximum brightness value. If the brightness value of the pixel is less than the maximum brightness value, then no compensation is applied. Alternatively the brightness value of the pixel may be compared with the maximum brightness value plus a threshold value. The invention stores correction values for a few pixels. If a particular pixel has a stored correction value, then this is subtracted from the brightness value of the particular pixel and the maximum brightness correction is applied to this difference. The stored correction value is replaced with the difference between the brightness value of the particular pixel and the maximum brightness value if this difference is greater than the stored correction value.
摘要翻译：本发明校正了成像器中的白点噪声。如果像素的亮度值大于八个周围像素的最大亮度值，则补偿的输出是该最大亮度值。如果像素的亮度值小于最大亮度值，则不进行补偿。或者，可以将像素的亮度值与最大亮度值加上阈值进行比较。本发明存储几个像素的校正值。如果特定像素具有存储的校正值，则从特定像素的亮度值中减去该像素，并且对该差异应用最大亮度校正。如果该差大于存储的校正值，则存储的校正值被替换为特定像素的亮度值与最大亮度值之间的差。

40. 发明授权

US06370191B1 Efficient implementation of error approximation in blind equalization of data communications 有权
标题翻译：数据通信盲均衡中误差近似的有效实现
公开(公告)号：US06370191B1
公开(公告)日：2002-04-09
申请号：US09431687
申请日：1999-11-01
申请人： Shivaling S. Mahant-Shetti , Srinath Hosur , Alan Gatherer
发明人： Shivaling S. Mahant-Shetti , Srinath Hosur , Alan Gatherer
IPC分类号： H04L2710
CPC分类号： G06F7/552 , G06F2207/5525 , H04L25/0307 , H04L2025/03401 , H04L2025/03477 , H04L2025/0349 , H04L2025/03573 , H04L2025/0363
摘要： A cable modem (20) having a blind equalizer (40) in its equalization function (28) is disclosed. The blind equalizer (40) includes an adaptive equalizer (44) and an approximating update function (42) that provides updated equalization coefficients to the adaptive equalizer (44) using the Constant Modulus Algorithm, wherein the error in the adaptive equalizer output is estimated. The estimates are based upon a determination of the maximum and minimum of the real and i components of symbols output by the adaptive equalizer (44). Efficiency in the computations required for updating the equalizer coefficients is obtained, without sacrificing convergence.
摘要翻译：公开了一种在其均衡功能（28）中具有盲均衡器（40）的电缆调制解调器（20）。盲均衡器（40）包括使用恒模算法向自适应均衡器（44）提供更新的均衡系数的自适应均衡器（44）和近似更新功能（42），其中估计自适应均衡器输出中的误差。估计基于由自适应均衡器（44）输出的符号的真实和i分量的最大值和最小值的确定。获得更新均衡器系数所需的计算的效率，而不会牺牲收敛。

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