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31. 发明授权

US06584029B2 One-time programmable memory using fuse/anti-fuse and vertically oriented fuse unit memory cells 失效
标题翻译：一次性可编程存储器，使用保险丝/反熔丝和垂直取向的熔丝单元存储单元
公开(公告)号：US06584029B2
公开(公告)日：2003-06-24
申请号：US09924577
申请日：2001-08-09
申请人： Lung T. Tran , Thomas C. Anthony , Frederick A. Perner
发明人： Lung T. Tran , Thomas C. Anthony , Frederick A. Perner
IPC分类号： G11C700
CPC分类号： H01L23/5252 , G11C13/0004 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A one-time programmable (“OTP”) memory includes one or more memory arrays stacked on top of each other. The OTP memory array is a cross-point array where unit memory cells are formed at the cross-points. The unit memory cell may include a fuse and an anti-fuse in series with each other or may include a vertically oriented fuse. Programming the memory may include the steps of selecting unit memory cells, applying a writing voltage such that critical voltage drop across the selected cells occur. This causes the anti-fuse of the cell to break down to a low resistance. The low resistance of the anti-fuse causes a high current pulse to be delivered to the fuse, which in turn melts the fuse to an open state. Reading the memory may include the steps of selecting unit memory cells for reading, applying a reading voltage to the selected memory cells and measuring whether current is present or not. Equipotential sensing may be used to read the memory.
摘要翻译：一次性可编程（“OTP”）存储器包括堆叠在彼此之上的一个或多个存储器阵列。 OTP存储器阵列是在交叉点处形成单位存储单元的交叉点阵列。单元存储单元可以包括彼此串联的保险丝和反熔丝，或者可以包括垂直定向的保险丝。对存储器进行编程可以包括选择单元存储器单元，施加写入电压以使得跨所选单元格出现临界电压降的步骤。这使得电池的反熔丝分解成低电阻。反熔丝的低电阻导致高电流脉冲被输送到保险丝，熔丝将熔丝熔化成打开状态。读取存储器可以包括以下步骤：选择用于读取的单元存储单元，向所选存储单元施加读取电压并测量是否存在电流。等电位感测可用于读取存储器。

32. 发明授权

US07248306B2 Method of making active matrix display 失效
标题翻译：制作有源矩阵显示的方法
公开(公告)号：US07248306B2
公开(公告)日：2007-07-24
申请号：US10897533
申请日：2004-07-23
申请人： Frederick A. Perner , Krzysztof Nauka
发明人： Frederick A. Perner , Krzysztof Nauka
IPC分类号： G02F1/136
CPC分类号： G02F1/1362 , G02F1/133305 , G02F1/1368 , G02F2001/136295
摘要： A method of making a lower cost active matrix display. In a particular embodiment, the method includes providing at least one first conductor upon a substrate and depositing a gate dielectric upon the first conductor and substrate. At least one paired second conductor and a pixel electrode are deposited upon the gate dielectric, with the second conductor crossing the first conductor and with a narrow gap between the paired second conductor and the pixel electrode. A semiconductor material is deposited over the paired second conductor and pixel electrode, filling the narrow gap. The narrow gap shelters a portion of the semiconductor material, which serves as a semiconductor bridge capable of functioning either as an insulator or as a channel region of a field effect transistor. The remaining, unsheltered semiconductor material is removed. A liquid crystal layer is then deposited upon the paired second conductor, the pixel electrode and the sheltered semiconductor material, and a translucent conductor is deposited upon the liquid crystal display layer. An associated display is also provided.
摘要翻译：制作成本较低的有源矩阵显示的方法。在特定实施例中，该方法包括在衬底上提供至少一个第一导体并在第一导体和衬底上沉积栅极电介质。至少一对成对的第二导体和像素电极沉积在栅极电介质上，其中第二导体与第一导体交叉并且在成对的第二导体和像素电极之间具有窄间隙。半导体材料沉积在成对的第二导体和像素电极上，填充窄间隙。窄间隙避开半导体材料的一部分，其用作能够用作场效应晶体管的绝缘体或沟道区的半导体桥。剩余的未加帽的半导体材料被去除。然后将液晶层沉积在成对的第二导体，像素电极和遮蔽半导体材料上，并且半透明导体沉积在液晶显示层上。还提供了相关联的显示。

33. 发明授权

US07242199B2 Active interconnects and control points in integrated circuits 有权
标题翻译：集成电路中的有源互连和控制点
公开(公告)号：US07242199B2
公开(公告)日：2007-07-10
申请号：US11112795
申请日：2005-04-21
申请人： R. Stanley Williams , Philip J Kuekes , Frederick A. Perner , Greg Snider , Duncan Stewart
发明人： R. Stanley Williams , Philip J Kuekes , Frederick A. Perner , Greg Snider , Duncan Stewart
IPC分类号： G01R27/08
CPC分类号： H05K7/1092 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： In various embodiments of the present invention, tunable resistors are introduced at the interconnect layer of integrated circuits in order to provide a for adjusting internal voltage and/or current levels within the integrated circuit to repair defective components or to configure the integrated circuit following manufacture. For example, when certain internal components, such as transistors, do not have specified electronic characteristics due to manufacturing defects, adjustment of the variable resistances of the tunable resistors included in the interconnect layer of integrated circuits according to embodiments of the present invention can be used to adjust internal voltage and/or levels in order to ameliorate the defective components. In other cases, the tunable resistors may be used as switches to configure integrated circuit components, including individual transistors and logic gates as well as larger, hierarchically structured functional modules and domains.
摘要翻译：在本发明的各种实施例中，在集成电路的互连层处引入可调电阻器，以便提供用于调整集成电路内的内部电压和/或电流水平以修复有缺陷的部件或者在制造之后配置集成电路。例如，当诸如晶体管的某些内部组件由于制造缺陷而没有指定的电子特性时，可以使用根据本发明的实施例的集成电路的互连层中包括的可调谐电阻的可变电阻的调整以调整内部电压和/或电平以便改善有缺陷的部件。在其他情况下，可调谐电阻器可以用作开关以配置集成电路部件，包括单独的晶体管和逻辑门以及更大的分层结构的功能模块和域。

34. 发明授权

US07180770B2 Series diode thermally assisted MRAM 有权
标题翻译：串联二极管热辅助MRAM
公开(公告)号：US07180770B2
公开(公告)日：2007-02-20
申请号：US11089688
申请日：2005-03-24
申请人： Frederick A. Perner , Janice Nickel , Lung Tran
发明人： Frederick A. Perner , Janice Nickel , Lung Tran
IPC分类号： G11C11/02
CPC分类号： G11C11/16 , G11C11/1675
摘要： An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.
摘要翻译：提供信息存储装置。信息存储装置可以是包括自旋相关隧道（SDT）结或磁存储元件的电阻交叉点阵列的磁性随机存取存储器（MRAM）装置，其中字线沿着沿着SDT结的行和沿着 SDT路口的列。本设计包括与相关联的磁存储元件串联连接的多个加热元件，每个加热元件包括二极管。施加到磁存储元件和相关联的加热元件的电压导致反向电流流过二极管，从而从二极管产生热量并加热磁存储元件，从而有助于器件的写入功能。

35. 发明授权

US07145797B2 Selecting a magnetic memory cell write current 有权
标题翻译：选择磁存储单元写入电流
公开(公告)号：US07145797B2
公开(公告)日：2006-12-05
申请号：US11003904
申请日：2004-12-03
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude of write current for writing to the magnetic memory cell, and calculating the selected magnitude of magnetic memory cell write current based on the minimal magnitude of write current and the maximal magnitude of write current.
摘要翻译：本发明包括用于选择磁存储单元写入电流的期望幅度的装置和方法。该方法包括确定用于写入磁存储器单元的写入电流的最小幅度，确定用于写入磁存储单元的写入电流的最大幅度，以及基于最小幅度来计算所选择的磁存储单元写入电流的大小写入电流和写入电流的最大幅度。

36. 发明授权

US07102948B2 Resistance change sensor 有权
标题翻译：电阻变化传感器
公开(公告)号：US07102948B2
公开(公告)日：2006-09-05
申请号：US10816482
申请日：2004-04-01
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C7/02
CPC分类号： G11C11/16 , G11C29/50 , G11C29/50008
摘要： An embodiment includes a resistance change sensor. The resistance change sensor includes a first input connected to a first resistance and a second input connected to a second resistance. The sensor further includes a resistance detector for sensing a resistive change in at least one of the first resistance and the second resistance.
摘要翻译：实施例包括电阻变化传感器。电阻变化传感器包括连接到第一电阻的第一输入和连接到第二电阻的第二输入。传感器还包括用于感测第一电阻和第二电阻中的至少一个电阻变化的电阻检测器。

37. 发明授权

US07102917B2 Memory array method and system 有权
标题翻译：内存阵列方法和系统
公开(公告)号：US07102917B2
公开(公告)日：2006-09-05
申请号：US10934718
申请日：2004-09-03
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C11/00 , G11C5/08 , G11C11/15 , G11C7/10 , G11C5/14 , G11C7/02
CPC分类号： G11C11/15
摘要： An MRAM memory array includes a set of memory cell strings wherein each memory cell string has a voltage divider input, a bit-sense output, a voltage divider ground, and a bit-sense output control, a shared switched voltage line that is capable of applying a voltage to the voltage divider inputs of the memory cell strings in the set, a common bit-sense line operatively coupled to the bit-sense outputs of the memory cell strings, a bit-sense output control line that is capable of selectively connecting the bit-sense output of a memory cell string to the common bit-sense line, and a ground operatively coupled to the voltage divider grounds of the voltage divider grounds.
摘要翻译： MRAM存储器阵列包括一组存储器单元串，其中每个存储器单元串具有分压器输入，位读出输出，分压器地和位读出输出控制，共享开关电压线能够对组中的存储器单元串的分压器输入施加电压，可操作地耦合到存储器单元串的位读出输出的公共位读取线，能够选择性地连接的位读出输出控制线存储器单元串到公共位读取线的位传输输出，以及可操作地耦合到分压器接地的分压器接地的地。

38. 发明授权

US07079438B2 Controlled temperature, thermal-assisted magnetic memory device 有权
标题翻译：受控温度，热辅助磁存储器件
公开(公告)号：US07079438B2
公开(公告)日：2006-07-18
申请号：US10779909
申请日：2004-02-17
申请人： Frederick A. Perner , Manoj K. Bhattacharyya
发明人： Frederick A. Perner , Manoj K. Bhattacharyya
IPC分类号： G11C7/04
CPC分类号： G11C11/15 , G11C11/1675
摘要： This invention provides a controlled temperature, thermal-assisted magnetic memory device. In a particular embodiment, there is an array of SVM cells, each characterized by an alterable orientation of magnetization and including a material wherein the coercivity is decreased upon an increase in temperature. In addition, at least one reference SVM (RSVM) cell substantially similar to and in close proximity to the SVM cells of the array is provided. A provided feedback control temperature controller receives a feedback voltage from the reference SVM cell, corresponding to temperature, and adjusts power applied to the RSVM cell and SVM cell. An associated method of use is further provided.
摘要翻译：本发明提供一种受控温度的热辅助磁存储器件。在特定实施例中，存在SVM单元阵列，每个SVM单元的特征在于磁化方向的可变方向，并且包括其中矫顽力在温度升高时降低的材料。此外，提供了与阵列的SVM单元基本相似并且非常接近的至少一个参考SVM（RSVM）单元。提供的反馈控制温度控制器从参考SVM单元接收对应于温度的反馈电压，并调整施加到RSVM单元和SVM单元的功率。还提供了相关联的使用方法。

39. 发明授权

US07079436B2 Resistive cross point memory 有权
标题翻译：电阻式交叉点存储器
公开(公告)号：US07079436B2
公开(公告)日：2006-07-18
申请号：US10675740
申请日：2003-09-30
申请人： Frederick A. Perner , Kenneth Kay Smith
发明人： Frederick A. Perner , Kenneth Kay Smith
IPC分类号： G11C7/02
CPC分类号： G11C29/02 , G11C7/02 , G11C11/1673 , G11C29/026 , G11C29/028 , G11C2207/2254
摘要： Embodiments of the present invention provide a resistive cross point memory. The resistive cross point memory comprises an array of memory cells and a read circuit. The read circuit is configured to sense a resistance through a memory cell in the array of memory cells to obtain a sense result and calibrate the read circuit based on the sensed result. The read circuit comprises an up/down counter that provides a calibration value to the read circuit.
摘要翻译：本发明的实施例提供一种电阻式交叉点存储器。电阻交叉点存储器包括存储器单元阵列和读取电路。读取电路被配置为感测通过存储器单元阵列中的存储器单元的电阻以获得感测结果，并且基于感测结果来校准读取电路。读取电路包括向读取电路提供校准值的向上/向下计数器。

40. 发明授权

US06961262B2 Memory cell isolation 失效
标题翻译：记忆体隔离
公开(公告)号：US06961262B2
公开(公告)日：2005-11-01
申请号：US10640792
申请日：2003-08-13
申请人： Frederick A. Perner
发明人： Frederick A. Perner
IPC分类号： G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , G11C11/00
CPC分类号： G11C11/16
摘要： Device and method for memory cell isolation. The memory cell includes a resistive component, such as a magnetic random access memory (MRAM) cell, and an isolation component, such as a four-layer diode. The memory cell may be included in a memory array. The method includes rapidly applying a forward bias across the isolation element to activate the isolation element.
摘要翻译：用于存储单元隔离的设备和方法。存储单元包括诸如磁性随机存取存储器（MRAM）单元的电阻元件以及诸如四层二极管的隔离元件。存储器单元可以被包括在存储器阵列中。该方法包括在隔离元件上快速施加正向偏压以激活隔离元件。

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