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31. 发明授权

US06199056B1 Apparatus for dividing an integer by 2n with over or under approximation 有权
标题翻译：用于将整数除以2n以上或近似的装置
公开(公告)号：US06199056B1
公开(公告)日：2001-03-06
申请号：US09174770
申请日：1998-10-19
申请人： Francesco Pappalardo , Vincenzo Matranga , Davide Tesi , Dario Di Bella
发明人： Francesco Pappalardo , Vincenzo Matranga , Davide Tesi , Dario Di Bella
IPC分类号： G06G700
CPC分类号： G06F7/49963 , G06F7/48 , G06N7/04 , Y10S706/90
摘要： An apparatus over or under approximates the result of dividing a binary number representing an integer 2n. The division by 2n is performed by truncating the n least significant bits of the integer. In order to over or under approximate the result, the nth truncated bit, i.e., the most significant bit of the n-truncated less significant bits, is added to the integer represented by the remaining non-truncated bits.
摘要翻译：超过或低于近似于表示整数2n的二进制数的结果的装置。通过截断整数的n个最低有效位来执行2n的除法。为了超过或低于近似结果，第n个截断位，即n个截断的较低有效位的最高有效位被添加到由剩余的非截断位表示的整数。

32. 发明授权

US08078804B2 Method and arrangement for cache memory management, related processor architecture 有权
标题翻译：高速缓存存储器管理方法与布置，相关处理器架构
公开(公告)号：US08078804B2
公开(公告)日：2011-12-13
申请号：US11768462
申请日：2007-06-26
申请人： Francesco Pappalardo , Giuseppe Notarangelo , Elena Salurso , Elio Guidetti
发明人： Francesco Pappalardo , Giuseppe Notarangelo , Elena Salurso , Elio Guidetti
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F15/00 , G06F15/76 , G06F9/30 , G06F9/40
CPC分类号： G06F12/084 , G06F12/0886 , Y02D10/13
摘要： A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.
摘要翻译：耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。数据位置以标量模式或矢量模式进行访问。这通过明确地映射标量的数据位置和矢量的数据位置来完成。

33. 发明授权

US07991081B2 Process and devices for transmitting digital signals over buses and computer program product therefore 有权
标题翻译：因此，通过总线和计算机程序产品传输数字信号的过程和设备
公开(公告)号：US07991081B2
公开(公告)日：2011-08-02
申请号：US12060809
申请日：2008-04-01
申请人： Francesco Pappalardo , Giuseppe Notarangelo
发明人： Francesco Pappalardo , Giuseppe Notarangelo
IPC分类号： H04L27/06
CPC分类号： G06F13/4072 , G06F13/4213
摘要： Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.
摘要翻译：数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定在前一时刻，以便最小化总线上的开关活动。

34. 发明授权

US07899860B2 Method and system for high-speed floating-point operations and related computer program product 有权
标题翻译：高速浮点运算方法与系统及相关计算机程序产品
公开(公告)号：US07899860B2
公开(公告)日：2011-03-01
申请号：US11190501
申请日：2005-07-26
申请人： Giuseppe Visalli , Francesco Pappalardo
发明人： Giuseppe Visalli , Francesco Pappalardo
IPC分类号： G06F7/50 , G06F15/00
CPC分类号： G06F7/74 , G06F7/485
摘要： A circuit for estimating propagated carries in an adder starting from operands that include actual addition inputs or at least one earlier carry, the circuit performs statistical circuit operations with independent binary traffic for the operands. Preferably, this binary traffic is independent and equiprobable or quasi-equiprobable binary traffic, and the adder is a leading zero anticipatory logic integer adder producing a number having the same number of leading zeroes as the result of the integer addition performed. The carry value may be produced from a logic function (e.g., Karnaugh Map, Quine-McClusky) of the operands, as a logic combination of the operands covering all the 1s in the logic function.
摘要翻译：一种用于从包括实际加法输入或至少一个较早进位的操作数开始的加法器中估计传播载波的电路，该电路用独立的二进制数据对操作数执行统计电路操作。优选地，该二进制流量是独立的和等能的或准等能的二进制流量，并且加法器是前导零预期逻辑整数加法器，其产生与执行的整数相加的结果相同数量的前导零的数字。进位值可以由操作数的逻辑功能（例如，Karnaugh Map，Quine-McClusky）产生，作为覆盖逻辑功能中的所有1的操作数的逻辑组合。

35. 发明授权

US07817763B2 Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权
标题翻译：用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法
公开(公告)号：US07817763B2
公开(公告)日：2010-10-19
申请号：US11787194
申请日：2007-04-12
申请人： Giuseppe Visalli , Francesco Pappalardo
发明人： Giuseppe Visalli , Francesco Pappalardo
IPC分类号： H04L25/38
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译：用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的，根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。

36. 发明授权

US07733396B2 Process and system for processing signals arranged in a bayer pattern 有权
标题翻译：用于处理以拜耳模式布置的信号的处理和系统
公开(公告)号：US07733396B2
公开(公告)日：2010-06-08
申请号：US10696396
申请日：2003-10-29
申请人： Francesco Pappalardo , Alessandro Capra , Massimo Mancuso , Hervé Broquin , Paolo Antonino Fodera , Elena Salurso
发明人： Francesco Pappalardo , Alessandro Capra , Massimo Mancuso , Hervé Broquin , Paolo Antonino Fodera , Elena Salurso
IPC分类号： H04N3/14 , H04N5/335 , H04N9/04 , H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： H04N1/648
摘要： Digital video signals, such as the signals generated by an image sensor in a Bayer format, are converted into an encoded format. In the Bayer format, the pixels of each line are alternately coded with two colors, and then converted into the encoded format. In the encoded format, the pixels of the digital video signals are reordered into sets of adjacent pixels, such that the sets group pixels coded with the same color. The encoded signal data results in a reduced switching activity when transmitted over a bus.
摘要翻译：诸如由拜耳格式的图像传感器产生的信号的数字视频信号被转换成编码格式。在拜耳格式中，每行的像素被交替地用两种颜色编码，然后被转换为编码格式。在编码格式中，将数字视频信号的像素重新排列成相邻像素的集合，使得组合像素以相同颜色编码。编码的信号数据在总线上传输时导致切换活动降低。

37. 发明授权

US07586943B2 Method and device for transmitting data on a single line, in particular for transmitting data on a bus with minimization of the bus switching activity, and corresponding computer product 有权
标题翻译：用于在单个线路上传输数据的方法和装置，特别是用于在总线上传输数据，同时最小化总线切换活动，以及对应的计算机产品
公开(公告)号：US07586943B2
公开(公告)日：2009-09-08
申请号：US10757772
申请日：2004-01-14
申请人： Francesco Pappalardo , Giuseppe Visalli
发明人： Francesco Pappalardo , Giuseppe Visalli
IPC分类号： H04J3/16
CPC分类号： G06F13/4286
摘要： Described herein is a method for transmitting data on a bus with minimization of the bus switching activity, comprising the steps of converting the datum to be transmitted from its own original format to a transmission format that minimizes the switching activity on the bus, said conversion consisting in swapping the position of one or more bits of the datum to be transmitted, the swapping being performable according to a plurality of different variants, each of which is identified by a respective sorting pattern, and selecting, between the various sorting patterns, an optimal sorting pattern that minimizes the bus switching activity upon transmission on the bus of the datum generated using said optimal sorting pattern.
摘要翻译：这里描述了一种用于在总线切换活动最小化的情况下在总线上发送数据的方法，包括以下步骤：将要发送的数据从其自己的原始格式转换成使总线上的切换活动最小化的传输格式，所述转换包括在交换要发送的数据的一个或多个比特的位置时，根据多个不同的变体进行交换，每个不同的变体由相应的分类模式标识，并且在各种分类模式之间选择最优排序模式，其使用所述最佳排序模式生成的基准总线上的传输最小化总线切换活动。

38. 发明授权

US07386006B2 Process and device for synchronization and codegroup identification in cellular communication systems and computer program therefor 有权
标题翻译：用于蜂窝通信系统中的同步和码组识别的过程和设备及其计算机程序
公开(公告)号：US07386006B2
公开(公告)日：2008-06-10
申请号：US10768400
申请日：2004-01-30
申请人： Francesco Rimi , Giuseppe Avellone , Francesco Pappalardo , Filippo Speziali , Agostino Galluzzo
发明人： Francesco Rimi , Giuseppe Avellone , Francesco Pappalardo , Filippo Speziali , Agostino Galluzzo
IPC分类号： H04J3/06 , H04B7/00
CPC分类号： H04B1/70735 , H04B1/7083 , H04B1/709 , H04B2201/70707
摘要： In a first step, slot synchronization may be obtained by setting in correlation the received signal with a primary sequence, which represents the primary channel, and storing the received signal. During a second step, the correlator may be re-used for correlating the received signal with a secondary sequence corresponding to the secondary synchronization codes. The correlator may include a first filter and a second filter connected in series, which receive a first secondary sequence and a second secondary sequence, which may include Golay sequences. Architectures of parallel and serial types, as well as architectures designed for reusing further circuit parts are also disclosed. The invention is particularly applicable in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, and WBCDMA.
摘要翻译：在第一步骤中，可以通过将接收到的信号与表示主信道的主序列进行相关设置并存储所接收的信号来获得时隙同步。在第二步骤期间，相关器可以被重新用于将接收的信号与对应于次级同步码的次级序列相关联。相关器可以包括串联连接的第一滤波器和第二滤波器，其接收可以包括格雷序列的第一次级序列和第二次级序列。还公开了并行和串行类型的架构，以及为再次使用其他电路部件而设计的架构。本发明特别适用于基于诸如UMTS，CDMA2000，IS95和WBCDMA的标准的移动通信系统。

39. 发明授权

US07352301B2 Method for transmitting a data flow over an optical bus, corresponding system and computer program product 有权
标题翻译：用于通过光学总线，对应的系统和计算机程序产品传输数据流的方法
公开(公告)号：US07352301B2
公开(公告)日：2008-04-01
申请号：US10963737
申请日：2004-10-12
申请人： Francesco Pappalardo , Giuseppe Notarangelo , Giuseppe Visalli
发明人： Francesco Pappalardo , Giuseppe Notarangelo , Giuseppe Visalli
IPC分类号： H03M5/00
CPC分类号： H04B10/5055 , H04B10/503 , H04B10/516 , H04B10/801 , H04L25/4915
摘要： A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.
摘要翻译：一种用于在光学连接上传送具有第一和第二逻辑状态的输入数据序列的方法，包括在光学连接上传输之前对输入数据序列进行编码，其中编码使编码数据序列中的第一逻辑状态最小化。编码包括：在多条总线上并行布置输入数据序列; 对输入数据序列中的第一逻辑状态进行计数; 将计数结果与等于一半行的值进行比较; 并且如果计数结果大于输入数据序列的行的一半，则对行上的输入数据序列进行逻辑反相。该方法还包括：排序输入数据序列的值; 识别具有第一逻辑状态的第一值; 以及将所述编码操作恰好应用于具有所述第一逻辑状态的所述第一值之后的有序值。

40. 发明申请

US20080037667A1 Processing method for providing, starting from signals acquired by a set of sensors, an aggregate signal and data acquisition system using such method 有权
标题翻译：用于从由一组传感器获取的信号开始，使用这种方法提供聚合信号和数据采集系统的处理方法
公开(公告)号：US20080037667A1
公开(公告)日：2008-02-14
申请号：US11787194
申请日：2007-04-12
申请人： Giuseppe Visalli , Francesco Pappalardo
发明人： Giuseppe Visalli , Francesco Pappalardo
IPC分类号： H04L27/28 , H04B1/10 , H04Q7/00
CPC分类号： H04L12/2856
摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.
摘要翻译：用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的，根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。

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