专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US07149132B2 Biasing circuit for use in a non-volatile memory device 有权
标题翻译：用于非易失性存储器件的偏置电路
公开(公告)号：US07149132B2
公开(公告)日：2006-12-12
申请号：US10948885
申请日：2004-09-24
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C16/30
CPC分类号： G11C8/08
摘要： A biasing circuit for use in a non-volatile memory device is coupled to the row decoder and to the column decoder to supply a first and at least a second biasing voltage for the word and bit lines, and includes a first voltage booster having a first input coupled to receive a supply voltage, a second input coupled to receive a reference voltage, and an output coupled to one of the row decoder and the column decoder to supply the first biasing voltage. A second voltage booster has a first input coupled to receive the supply voltage, a second input coupled to the output of the first voltage booster to receive the first biasing voltage, and an output coupled to the other of the row decoder and the column decoder to supply the second biasing voltage.
摘要翻译：用于非易失性存储器件的偏置电路耦合到行解码器和列解码器，以为字和位线提供第一和至少第二偏置电压，并且包括第一电压升压器，其具有第一耦合以接收电源电压的输入，耦合以接收参考电压的第二输入，以及耦合到行解码器和列解码器之一以提供第一偏置电压的输出。第二电压升压器具有耦合以接收电源电压的第一输入，耦合到第一电压升压器的输出以接收第一偏置电压的第二输入，以及耦合到行解码器和列解码器中的另一个的输出提供第二偏置电压。

32. 发明授权

US07020014B2 Circuit and method for temperature tracing of devices including an element of chalcogenic material, in particular phase change memory devices 有权
标题翻译：用于包括硫属元素元素的装置的温度追踪的电路和方法，特别是相变存储器件
公开(公告)号：US07020014B2
公开(公告)日：2006-03-28
申请号：US10715883
申请日：2003-11-18
申请人： Osama Khouri , Ferdinando Bedeschi , Claudio Resta
发明人： Osama Khouri , Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C11/00
CPC分类号： G11C7/04 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2029/5002 , G11C2213/79
摘要： A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor of chalcogenic material furnishing an electrical quantity that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor has the same structure as a memory cell and is programmed with precision, preferably in the reset state.
摘要翻译：相变存储器包括具有与相变存储元件相同定律的具有温度的电阻变化的温度传感器。该温度传感器是由一个硫化物材料的电阻器形成的，它提供一个再现相变存储器单元电阻和温度之间的关系的电量; 对电量进行处理，以便产生写入和读取存储单元所需的参考量。硫属电阻器具有与存储器单元相同的结构，并且精确地编程，优选地处于复位状态。

33. 发明申请

US20050041498A1 Writing circuit for a phase change memory device 有权
标题翻译：写相电路用于相变存储器件
公开(公告)号：US20050041498A1
公开(公告)日：2005-02-24
申请号：US10870694
申请日：2004-06-16
申请人： Claudio Resta , Ferdinando Bedeschi , Fabio Pellizzer , Giulio Casagrande
发明人： Claudio Resta , Ferdinando Bedeschi , Fabio Pellizzer , Giulio Casagrande
IPC分类号： G11C7/00 , G11C11/34 , G11C16/02 , G11C16/10
CPC分类号： G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.
摘要翻译：一种相变型存储器件，其中存储器单元具有可在存储器单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件。写入级连接到存储单元，并且具有被配置为产生没有恒定部分的放电电流并使存储器单元改变状态的电容电路。

34. 发明授权

US07675792B2 Generating reference currents compensated for process variation in non-volatile memories 有权
标题翻译：生成参考电流补偿了非易失性存储器中的工艺变化
公开(公告)号：US07675792B2
公开(公告)日：2010-03-09
申请号：US11904071
申请日：2007-09-26
申请人： Ferdinando Bedeschi , Claudio Resta , Enzo Donze
发明人： Ferdinando Bedeschi , Claudio Resta , Enzo Donze
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： In a current reference generator device, a voltage reference generator stage generates a reference voltage (Vref) and an active element output stage receives the reference voltage (Vref) and outputs a reference current (Iref) as a function of the reference voltage (Vref). A control stage is operatively coupled to the voltage reference generator stage and to the active element output stage and controls a first trimmable parameter (m) associated to the voltage reference generator stage and a second trimmable parameter associated to the active element output stage, so as to compensate for changes in a value of the reference current (Iref) due to manufacturing process deviations.
摘要翻译：在电流参考发生器装置中，电压基准发生器级产生参考电压（Vref），并且有源元件输出级接收参考电压（Vref）并输出作为参考电压（Vref）的函数的参考电流（Iref）。控制级可操作地耦合到电压参考发生器级和有源元件输出级，并且控制与电压参考发生器级相关联的第一可调整参数（m）和与有源元件输出级相关联的第二可调整参数，以便以补偿由于制造工艺偏差导致的参考电流（Iref）的值的变化。

35. 发明申请

US20090091988A1 Writing bit alterable memories 有权
标题翻译：写点可变记忆
公开(公告)号：US20090091988A1
公开(公告)日：2009-04-09
申请号：US11906722
申请日：2007-10-03
申请人： Ferdinando Bedeschi , Claudio Resta , Richard Fackenthal , Ruili Zhang
发明人： Ferdinando Bedeschi , Claudio Resta , Richard Fackenthal , Ruili Zhang
IPC分类号： G11C5/14
CPC分类号： G11C5/145
摘要： A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients.
摘要翻译：一个可变的存储器可以包括在主存储器核心外部的周边的电流发生器。电流可能在外围产生并被驱动到芯中。结果，存储单元的电容降低了效果。可以使用芯片电源电压产生电流，然后使用泵浦电压进行镜像。在一些实施例中，镜像可以在分区级别进行比例并且在平面级上相乘。在将电流施加到电池以适应瞬态之前可以提供延迟。

36. 发明授权

US07075841B2 Writing circuit for a phase change memory device 有权
标题翻译：写相电路用于相变存储器件
公开(公告)号：US07075841B2
公开(公告)日：2006-07-11
申请号：US10870694
申请日：2004-06-16
申请人： Claudio Resta , Ferdinando Bedeschi , Fabio Pellizzer , Giulio Casagrande
发明人： Claudio Resta , Ferdinando Bedeschi , Fabio Pellizzer , Giulio Casagrande
IPC分类号： G11C7/00
CPC分类号： G11C13/0004 , G11C13/0038 , G11C13/0069 , G11C2013/0078 , G11C2213/79
摘要： A memory device of a phase change type, wherein a memory cell has a memory element of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage is connected to the memory cell and has a capacitive circuit configured to generate a discharge current having no constant portion and to cause the memory cell to change state.
摘要翻译：一种相变型存储器件，其中存储器单元具有可在存储器单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件。写入级连接到存储单元，并且具有被配置为产生没有恒定部分的放电电流并使存储器单元改变状态的电容电路。

37. 发明授权

US07068534B2 Phase-change memory device with overvoltage protection and method for protecting a phase-change memory device against overvoltages 有权
标题翻译：具有过电压保护的相变存储器件和用于保护相变存储器件免受过电压的方法
公开(公告)号：US07068534B2
公开(公告)日：2006-06-27
申请号：US10987933
申请日：2004-11-12
申请人： Ferdinando Bedeschi , Claudio Resta , Guido Torelli
发明人： Ferdinando Bedeschi , Claudio Resta , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C13/0059 , G11C2013/0054 , G11C2213/79
摘要： A phase change memory device includes a plurality of phase-change memory cells, arranged in rows and columns, phase-change memory cells arranged on the same column being connected to a same bit line; a plurality of first selectors, each coupled to a respective phase-change memory cell; an addressing circuit for selectively addressing at least one of the bit lines, one of the first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector; and a regulated voltage supply circuit, selectively connectable to the addressed bit line, for supplying a bit line voltage. The bit line voltage is correlated to a first control voltage on the addressed first selector, coupled to the addressed phase-change memory cell.
摘要翻译：相变存储器件包括排列成行和列的多个相变存储器单元，布置在同一列上的相变存储器单元连接到相同的位线; 多个第一选择器，每个耦合到相应的相变存储单元; 寻址电路，用于选择性地寻址至少一个位线，第一选择器中的一个以及连接到寻址位线和寻址的第一选择器的相变存储器单元; 以及可选择地连接到寻址的位线的稳压电源电路，用于提供位线电压。位线电压与寻址的第一选择器上的第一控制电压相关，耦合到寻址的相变存储单元。

38. 发明申请

US20050185572A1 Fast reading, low consumption memory device and reading method thereof 有权
标题翻译：快速阅读，低消耗记忆装置及其阅读方法
公开(公告)号：US20050185572A1
公开(公告)日：2005-08-25
申请号：US11018550
申请日：2004-12-20
申请人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
发明人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
IPC分类号： G11C7/12 , G11C8/10 , G11C11/34 , G11C16/02 , G11C16/08 , H04J3/07
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.
摘要翻译：一种存储器件，具有读取配置，并且包括排列成行和列的多个存储器单元，布置在同一列上的存储器单元具有连接到相同位线的相应第一端子和布置在同一行上的存储器单元，该存储单元具有相应的第二端子可选择性地连接到相同的字线; 提供电源电压的电源线; 列寻址电路和行寻址电路，用于分别寻址与读取配置中读取的存储单元对应的位线和字线。列寻址电路被配置为在读取配置中基本上以电源电压偏置对应于所选存储单元的寻址位线。行驱动电路以非零字线读取电压偏置对应于所选存储单元的寻址字线，使得在第一端和第二端之间施加低于相变电压的预定电池电压读取配置中选定的存储单元。

39. 发明授权

US09070473B2 Refresh architecture and algorithm for non-volatile memories 有权
标题翻译：刷新非易失性存储器的架构和算法
公开(公告)号：US09070473B2
公开(公告)日：2015-06-30
申请号：US13513139
申请日：2009-12-02
申请人： Ferdinando Bedeschi , Roberto Gastaldi
发明人： Ferdinando Bedeschi , Roberto Gastaldi
IPC分类号： G11C11/00 , G11C16/34 , G11C13/00 , G11C11/56
CPC分类号： G11C13/0033 , G06F11/1068 , G11C11/5678 , G11C13/0004 , G11C13/0038 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C14/009 , G11C16/3418 , G11C29/52
摘要： Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.
摘要翻译：刷新非易失性存储器件的方法和系统，例如相变存储器。在一个实施例中，作为系统状态的函数，存储器设备使用边缘读取参考电平或使用非余量读取参考电平对错误校正的存储器单元的第二刷新来执行存储器单元的第一刷新。

40. 发明申请

US20140376306A1 METHODS FOR A PHASE-CHANGE MEMORY ARRAY 有权
标题翻译：相变记忆阵列的方法
公开(公告)号：US20140376306A1
公开(公告)日：2014-12-25
申请号：US13518361
申请日：2009-12-31
申请人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
发明人： Ferdinando Bedeschi , Claudio Resta , Marco Ferraro
IPC分类号： G11C13/00
CPC分类号： G06F3/0622 , G06F3/0643 , G06F3/0679 , G11C13/0004 , G11C13/004 , G11C13/0059 , G11C13/0069 , G11C13/0097 , G11C13/02 , H01L45/04 , H01L45/06
摘要： Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and executing, according to the pattern, two or more proper reset sequences on the phase-change memory array to write the pattern to the phase-change memory array. Another method includes executing a set sequence on a phase-change memory array and performing a proper read of the phase-change memory array to obtain a pattern derived from executing the set sequence.
摘要翻译：描述了操作相变存储器阵列的方法。一种方法包括确定要写入相变存储器阵列的图案，并且根据该图案，在相变存储器阵列上执行两个或更多个适当的复位序列以将该图案写入相变存储器阵列。另一种方法包括在相变存储器阵列上执行设置序列并执行相变存储器阵列的适当读取以获得从执行所述设置序列导出的模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式