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31. 发明授权

US07068534B2 Phase-change memory device with overvoltage protection and method for protecting a phase-change memory device against overvoltages 有权
标题翻译：具有过电压保护的相变存储器件和用于保护相变存储器件免受过电压的方法
公开(公告)号：US07068534B2
公开(公告)日：2006-06-27
申请号：US10987933
申请日：2004-11-12
申请人： Ferdinando Bedeschi , Claudio Resta , Guido Torelli
发明人： Ferdinando Bedeschi , Claudio Resta , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0026 , G11C13/004 , G11C13/0059 , G11C2013/0054 , G11C2213/79
摘要： A phase change memory device includes a plurality of phase-change memory cells, arranged in rows and columns, phase-change memory cells arranged on the same column being connected to a same bit line; a plurality of first selectors, each coupled to a respective phase-change memory cell; an addressing circuit for selectively addressing at least one of the bit lines, one of the first selectors, and the phase-change memory cell connected to the addressed bit line and to the addressed first selector; and a regulated voltage supply circuit, selectively connectable to the addressed bit line, for supplying a bit line voltage. The bit line voltage is correlated to a first control voltage on the addressed first selector, coupled to the addressed phase-change memory cell.
摘要翻译：相变存储器件包括排列成行和列的多个相变存储器单元，布置在同一列上的相变存储器单元连接到相同的位线; 多个第一选择器，每个耦合到相应的相变存储单元; 寻址电路，用于选择性地寻址至少一个位线，第一选择器中的一个以及连接到寻址位线和寻址的第一选择器的相变存储器单元; 以及可选择地连接到寻址的位线的稳压电源电路，用于提供位线电压。位线电压与寻址的第一选择器上的第一控制电压相关，耦合到寻址的相变存储单元。

32. 发明申请

US20050185572A1 Fast reading, low consumption memory device and reading method thereof 有权
标题翻译：快速阅读，低消耗记忆装置及其阅读方法
公开(公告)号：US20050185572A1
公开(公告)日：2005-08-25
申请号：US11018550
申请日：2004-12-20
申请人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
发明人： Claudio Resta , Ferdinando Bedeschi , Guido Torelli
IPC分类号： G11C7/12 , G11C8/10 , G11C11/34 , G11C16/02 , G11C16/08 , H04J3/07
CPC分类号： G11C13/0004 , G11C7/12 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004
摘要： A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.
摘要翻译：一种存储器件，具有读取配置，并且包括排列成行和列的多个存储器单元，布置在同一列上的存储器单元具有连接到相同位线的相应第一端子和布置在同一行上的存储器单元，该存储单元具有相应的第二端子可选择性地连接到相同的字线; 提供电源电压的电源线; 列寻址电路和行寻址电路，用于分别寻址与读取配置中读取的存储单元对应的位线和字线。列寻址电路被配置为在读取配置中基本上以电源电压偏置对应于所选存储单元的寻址位线。行驱动电路以非零字线读取电压偏置对应于所选存储单元的寻址字线，使得在第一端和第二端之间施加低于相变电压的预定电池电压读取配置中选定的存储单元。

33. 发明授权

US08565031B2 Method for reading phase change memory cells having a clamping circuit 有权
标题翻译：读取具有钳位电路的相变存储单元的方法
公开(公告)号：US08565031B2
公开(公告)日：2013-10-22
申请号：US13561172
申请日：2012-07-30
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C7/06
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C2013/0054 , G11C2211/5645 , G11C2213/79
摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.
摘要翻译：一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

34. 发明申请

US20120113711A1 Using A Bit Specific Reference Level To Read A Memory 有权
标题翻译：使用位特定参考电平读取存储器
公开(公告)号：US20120113711A1
公开(公告)日：2012-05-10
申请号：US13353531
申请日：2012-01-19
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C11/00 , G11C5/14 , G11C7/06
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments,
摘要翻译：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。在一些实施例中，可以改善所得到的读取窗口或边缘，

35. 发明授权

US08116159B2 Using a bit specific reference level to read a resistive memory 有权
标题翻译：使用特定的参考电平读取电阻性存储器
公开(公告)号：US08116159B2
公开(公告)日：2012-02-14
申请号：US11093877
申请日：2005-03-30
申请人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
发明人： Tyler Lowrey , Ward D. Parkinson , Ferdinando Bedeschi , Claudio Resta , Roberto Gastaldi , Giulio Casagrande
IPC分类号： G11C7/14
CPC分类号： G11C7/14 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments.
摘要翻译：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。在一些实施例中，可以改善所得到的读取窗口或边缘。

36. 发明授权

US08098512B2 Reading phase change memories 有权
标题翻译：阅读相变记忆
公开(公告)号：US08098512B2
公开(公告)日：2012-01-17
申请号：US13072911
申请日：2011-03-28
申请人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
发明人： Ward D. Parkinson , Giulio Casagrande , Claudio Resta , Roberto Gastaldi , Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/5678 , G11C13/0004 , G11C13/003 , G11C2013/0045 , G11C2013/0054 , G11C2013/0066 , G11C2213/75 , G11C2213/76
摘要： A read current high enough to threshold a phase change memory element may be used to read the element without thresholding the memory element. The higher current may improve performance in some cases. The memory element does not threshold because the element is read and the current stopped prior to triggering the memory element.
摘要翻译：可以使用高达阈值相变存储器元件的读取电流来读取元件而不对存储元件进行阈值化。在某些情况下，较高的电流可能会改善性能。由于读取元素并且在触发存储器元件之前停止了当前存储器元件，因此存储器元件不会被阈值。

37. 发明授权

US08026757B2 Current mirror circuit, in particular for a non-volatile memory device 有权
标题翻译：电流镜电路，特别是用于非易失性存储器件
公开(公告)号：US08026757B2
公开(公告)日：2011-09-27
申请号：US12570770
申请日：2009-09-30
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C11/4074 , H03K17/687 , G05F3/26
CPC分类号： G05F3/26
摘要： A current mirror circuit is provided with a first current mirror including first and second mirror transistors sharing a common control terminal; the first mirror transistor has a conduction terminal for receiving, during a first operating condition, a first reference current, and the second mirror transistor has a respective conduction terminal for providing, during the first operating condition, a mirrored current based on the first reference current. The current mirror circuit is provided with a switching stage operable to connect the control terminal to the conduction terminal of the first mirror transistor during the first operating condition, and to disconnect the control terminal from the same conduction terminal of the first mirror transistor, and either letting it substantially float or connecting it to a reference voltage, during a second operating condition, in particular a condition of stand-by.
摘要翻译：电流镜电路设置有第一电流镜，其包括共享公共控制端的第一和第二镜像晶体管; 第一反射镜晶体管具有用于在第一操作条件期间接收第一参考电流的导电端子，并且第二反射镜晶体管具有相应的导通端子，用于在第一操作条件期间提供基于第一参考电流的镜像电流。电流镜电路设置有开关级，可操作以在第一操作状态期间将控制端连接到第一镜晶体管的导通端，并且将控制端与第一镜晶体管的相同导通端断开，在第二操作条件下，特别是待机状态，使其基本上浮动或将其连接到参考电压。

38. 发明授权

US07869267B2 Method for low power accessing a phase change memory device 有权
标题翻译：用于低功率访问相变存储器件的方法
公开(公告)号：US07869267B2
公开(公告)日：2011-01-11
申请号：US12345411
申请日：2008-12-29
申请人： Claudio Resta , Ferdinando Bedeschi
发明人： Claudio Resta , Ferdinando Bedeschi
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C8/10 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2213/79
摘要： A method for accessing a phase change memory device, wherein a first sub-plurality of bitlines is grouped in a first group and a second sub-plurality of bitlines is grouped in a second group. At least a bitline in the first and second groups are selected; currents are supplied to the selected bitlines; and a selected wordline is biased. The bitlines are selected by selecting a first bitline in the first group and, while the first bitline is selected, selecting a second bitline in the second group which is arranged on the selected wordline symmetrically to the first bitline in the first group.
摘要翻译：一种用于访问相变存储器件的方法，其中第一组多个位线被分组在第一组中，并且第二副多个位线被分组在第二组中。至少选择第一和第二组的位线; 电流被提供给选定的位线; 并且选定的字线有偏见。通过选择第一组中的第一位线来选择位线，并且在选择第一位线的同时，在第二组中选择布置在所选择的字线上的与第一组中的第一位线对称的第二位线。

39. 发明申请

US20100284212A1 METHOD FOR MULTILEVEL PROGRAMMING OF PHASE CHANGE CELLS USING ADAPTIVE RESET PULSES 有权
标题翻译：使用自适应复位脉冲进行相位变化的多重编程的方法
公开(公告)号：US20100284212A1
公开(公告)日：2010-11-11
申请号：US12780580
申请日：2010-05-14
申请人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
发明人： Ferdinando Bedeschi , Claudio Resta , Enzo Michele Donze , Roberto Gastaldi , Alessandro Cabrini , Guido Torelli
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C2013/0076 , G11C2013/0092
摘要： A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.
摘要翻译：用于编程多电平PCM单元的方法设想：通过施加一个或多个复位脉冲，在PCM单元的存储元件中形成非晶相变材料的非晶区域; 以及通过施加一个或多个设定脉冲，形成所述PCM单元的编程状态的导电路径的大小和与其相关联的输出电量，并通过所述值来控制所述晶体相变材料的导电路径通过所述非晶区域的复位脉冲和设定脉冲。形成非晶区域的步骤设想在编程操作期间自适应地和迭代地确定针对PCM单元的电气和/或物理特性优化的复位脉冲的值，特别是确定复位脉冲的最小振幅值，这允许编程期望的编程状态和输出电量的期望值。

40. 发明授权

US07570524B2 Circuitry for reading phase change memory cells having a clamping circuit 有权
标题翻译：用于读取具有钳位电路的相变存储单元的电路
公开(公告)号：US07570524B2
公开(公告)日：2009-08-04
申请号：US11093879
申请日：2005-03-30
申请人： Ferdinando Bedeschi , Claudio Resta
发明人： Ferdinando Bedeschi , Claudio Resta
IPC分类号： G11C7/08
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/004 , G11C2013/0054 , G11C2211/5645 , G11C2213/79
摘要： A read circuit for reading at least one memory cell adapted to storing a logic value, the at least one memory cell including: a storage element made of a phase-change material; and an access element for coupling the storage element to the read circuit in response to a selection of the memory cell, the read circuit including: a sense current supply arrangement for supplying a sense current to the at least one memory cell; and at least one sense amplifier for determining the logic value stored in the memory cell on the basis of a voltage developing thereacross, the at least one sense amplifier comprising a voltage limiting circuit for limiting the voltage across the memory cell for preserving the stored logic value, wherein the voltage limiting circuit includes a current sinker for sinking a clamping current, which is subtracted from the sense current and depends on the stored logic value.
摘要翻译：一种用于读取适于存储逻辑值的至少一个存储单元的读取电路，所述至少一个存储单元包括：由相变材料制成的存储元件; 以及用于响应于所述存储单元的选择将所述存储元件耦合到所述读取电路的访问元件，所述读取电路包括：用于向所述至少一个存储器单元提供感测电流的感测电流供应装置; 以及至少一个读出放大器，用于基于在其上形成的电压来确定存储在存储器单元中的逻辑值，所述至少一个读出放大器包括用于限制存储器单元两端的电压的电压限制电路，用于保存所存储的逻辑值其中所述电压限制电路包括用于吸收钳位电流的电流沉降片，其从所述感测电流中减去并且取决于所存储的逻辑值。

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