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31. 发明申请

US20170192781A1 Systems, Apparatuses, and Methods for Strided Loads 审中-公开
公开(公告)号：US20170192781A1
公开(公告)日：2017-07-06
申请号：US14984124
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30043 , G06F9/30098 , G06F9/30109 , G06F9/30112 , G06F9/30192 , G06F9/3455
摘要： Detailed herein are systems, apparatuses, and methods for strided loads. In an embodiment, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a starting destination register operand; and execution circuitry to execute the decoded instruction to extract data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, store the extracted data elements in a packed data register dedicated to that type beginning with starting destination register operand.

32. 发明申请

US20170192780A1 Systems, Apparatuses, and Methods for Getting Even and Odd Data Elements 审中-公开
公开(公告)号：US20170192780A1
公开(公告)日：2017-07-06
申请号：US14984078
申请日：2015-12-30
申请人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
发明人： Robert Valentine , Elmoustapha Ould-Ahmed-Vall , Jason W. Brandt , Mark J. Charney , Ashish Jha , Milind B. Girkar , Bret L. Toll , Evgeny V. Stupachenko , Sergey Y. Ostanevich
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30101 , G06F9/30192
摘要： Embodiments of systems, apparatuses, and method for getting even or odd data elements are described. For example, in some embodiments, an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields for a first source operand, a second source operand, and a destination operand; and execution circuitry to execute the decoded instruction to extract data elements from even data element positions of the first and second source operands and store the extracted data elements into the destination operand.

33. 发明申请

US20140149724A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：US20140149724A1
公开(公告)日：2014-05-29
申请号：US14170397
申请日：2014-01-31
申请人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
发明人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30149 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

34. 发明申请

US20160196139A1 SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING A SHUFFLE AND OPERATION (SHUFFLE-OP) 审中-公开
标题翻译：用于执行机器人和操作的系统，设备和方法（SHUFFLE-OP）
公开(公告)号：US20160196139A1
公开(公告)日：2016-07-07
申请号：US14981885
申请日：2015-12-28
申请人： Igor Ermolaev , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll , Jesus Corbal San Adrian , Andrey Naraikin
发明人： Igor Ermolaev , Elmoustapha Ould-Ahmed-Vall , Bret L. Toll , Jesus Corbal San Adrian , Andrey Naraikin
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30029 , G06F9/30032 , G06F9/30098 , G06F9/30145 , G06F9/3016
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor a data element shuffle and an operation on the shuffled data elements in response to a single data element shuffle and an operation instruction that includes a destination vector register operand, a first and second source vector register operands, an immediate value, and an opcode are described.
摘要翻译：用于在计算机处理器中响应于单个数据元素随机播放的数据元素随机播放和对混洗数据元素的操作的系统，装置和方法的实施例，以及包括目的地向量寄存器操作数，第一和第二描述源向量寄存器操作数，立即值和操作码。

35. 发明申请

US20130305020A1 VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF 审中-公开
标题翻译：向导友好指示格式及其执行
公开(公告)号：US20130305020A1
公开(公告)日：2013-11-14
申请号：US13976707
申请日：2011-09-30
申请人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
发明人： Robert C. Valentine , Jesus Corbal San Adrian , Roger Espasa Sans , Robert D. Cavin , Bret L. Toll , Santiago Galan Duran , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Edward Thomas Grochowski , Jonathan Cannon Hall , Dennis R. Bradford , Elmoustapha Ould-Ahmed-Vall , James C. Abel , Mark Charney , Seth Abraham , Suleyman Sair , Andrew Thomas Forsyth , Lisa Wu , Charles Yount
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30047 , G06F9/30149 , G06F9/30181 , G06F9/30185 , G06F9/30192 , G06F9/34
摘要： A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
摘要翻译：一种向量友好的指令格式及其执行。根据本发明的一个实施例，处理器被配置为执行指令集。指令集包括向量友好指令格式。向量友好指令格式具有多个字段，包括基本操作字段，修改字段，增加操作字段和数据元素宽度字段，其中第一指令格式支持不同版本的基本操作和不同的扩充操作，基本操作字段，修饰符字段，α字段，β字段和数据元素宽度字段中的不同值，并且其中只有一个不同的值可以被放置在基本操作字段，修饰符字段，在指令流中的第一指令格式的指令的每次出现时的alpha字段，β字段和数据元素宽度字段。

36. 发明申请

US20120254588A1 SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK 审中-公开
标题翻译：使用WRITEMASK将两个源操作混合到单个目的地的系统，设备和方法
公开(公告)号：US20120254588A1
公开(公告)日：2012-10-04
申请号：US13078864
申请日：2011-04-01
申请人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
发明人： Jesus Corbal San Adrian , Bret L. Toll , Robert C. Valentine , Jeffrey G. Wiedemeier , Sridhar Samudrala , Milind Baburao Girkar , Andrew Thomas Forsyth , Elmoustapha Ould-Ahmed-Vall , Dennis R. Bradford , Lisa K. Wu
IPC分类号： G06F9/30
CPC分类号： G06F9/30192 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.
摘要翻译：描述了用于在计算机处理器中执行混合指令的系统，装置和方法的实施例。在一些实施例中，混合指令的执行使用作为第一操作数和第二操作数之间的选择器的写入掩码的相应比特位置，逐个元素地选择第一和第二源操作数的数据元素，并存储所选择的数据元素到达目的地的目标位置。

37. 发明申请

US20120185670A1 SCALAR INTEGER INSTRUCTIONS CAPABLE OF EXECUTION WITH THREE REGISTERS 审中-公开
标题翻译：标准整数指令可执行三个注册
公开(公告)号：US20120185670A1
公开(公告)日：2012-07-19
申请号：US13007050
申请日：2011-01-14
申请人： Bret L. Toll , Robert Valentine , Maxim Locktyukhin , Elmoustapha Ould-Ahmed-Vall
发明人： Bret L. Toll , Robert Valentine , Maxim Locktyukhin , Elmoustapha Ould-Ahmed-Vall
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/30036 , G06F9/3012 , G06F9/3016 , G06F9/30185
摘要： A processing core implemented on a semiconductor chip is described. The processing core includes logic circuitry to identify whether vector instructions and integer scalar instructions are to be executed with two registers or three registers, where, in the case of two registers input operand information is destroyed in one of two registers, and, in the case of three registers input operand is not destroyed. The processing core also includes steering circuitry coupled to the logic circuitry. The steering circuitry is to control first data paths between scalar integer execution units and a scalar integer register bank such that two registers are accessed from the scalar register bank if two register execution is identified for the scalar integer instructions or three registers are accessed from the scalar integer register bank if three register execution is identified for the scalar integer instructions. The steering circuitry is also to control second data paths between vector execution units and a vector register bank such that two registers are accessed from the vector register bank if two register execution is identified for the vector instructions or three registers are accessed from the vector register bank if three register execution is identified for the vector instructions.
摘要翻译：描述了在半导体芯片上实现的处理核心。处理核心包括用于识别矢量指令和整数标量指令是否要用两个寄存器或三个寄存器执行的逻辑电路，其中在两个寄存器的情况下输入操作数信息在两个寄存器之一中被销毁，并且在这种情况下的三个寄存器输入操作数不会被破坏。处理核心还包括耦合到逻辑电路的转向电路。转向电路是控制标量整数执行单元和标量整数寄存器组之间的第一数据路径，以便如果为标量整数指令识别两个寄存器执行，则从标量寄存器组访问两个寄存器，或者从标量访问三个寄存器整数寄存器组如果为标量整数指令标识了三个寄存器执行。转向电路还用于控制向量执行单元和向量寄存器组之间的第二数据路径，使得如果为向量指令识别了两个寄存器执行，则从向量寄存器组访问两个寄存器，或者从向量寄存器组访问三个寄存器如果为向量指令识别了三个寄存器执行。

38. 发明申请

US20130318328A1 APPARATUS AND METHOD FOR SHUFFLING FLOATING POINT OR INTEGER VALUES 有权
标题翻译：浮动点或整数值的装置和方法
公开(公告)号：US20130318328A1
公开(公告)日：2013-11-28
申请号：US13997244
申请日：2011-12-23
申请人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Tal Uliel , Bret L. Toll
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30018 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method are described for shuffling data elements from source registers to a destination register. For example, a method according to one embodiment includes the following operations: reading each mask bit stored in a mask data structure, the mask data structure containing mask bits associated with data elements of a destination register, the values usable for determining whether a masking operation or a shuffle operation should be performed on data elements stored within a first source register and a second source register; for each data element of the destination register, if a mask bit associated with the data element indicates that a shuffle operation should be performed, then shuffling data elements from the first source register and the second source register to the specified data element within the destination register; and if the mask bit indicates that a masking operation should be performed, then performing a specified masking operation with respect to the data element of the destination register.
摘要翻译：描述了将数据元素从源寄存器混合到目的地寄存器的装置和方法。例如，根据一个实施例的方法包括以下操作：读取存储在掩模数据结构中的每个掩码位，所述掩码数据结构包含与目的地寄存器的数据元素相关联的掩码位，可用于确定掩蔽操作或者应当对存储在第一源寄存器和第二源寄存器中的数据元素执行混洗操作; 对于目标寄存器的每个数据元素，如果与数据元素相关联的掩码位指示应当执行混洗操作，则将数据元素从第一源寄存器和第二源寄存器混洗到目标寄存器中的指定数据元素 ; 并且如果掩码位指示应当执行掩蔽操作，则对目的地寄存器的数据元素执行指定的掩蔽操作。

39. 发明申请

US20140281401A1 Systems, Apparatuses, and Methods for Determining a Trailing Least Significant Masking Bit of a Writemask Register 有权
标题翻译：用于确定写掩码寄存器的尾随最低有效屏蔽位的系统，设备和方法
公开(公告)号：US20140281401A1
公开(公告)日：2014-09-18
申请号：US13840809
申请日：2013-03-15
申请人： Christopher J. Hughes , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Elmoustapha Ould-Ahmed_Vall , Bret L. Toll , Robert Valentine
发明人： Christopher J. Hughes , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Elmoustapha Ould-Ahmed_Vall , Bret L. Toll , Robert Valentine
IPC分类号： G06F9/30
CPC分类号： G06F9/30152 , G06F9/30018 , G06F9/30036
摘要： The execution of a KZBTZ finds a trailing least significant zero bit position in an first input mask and sets an output mask to have the values of the first input mask, but with all bit positions closer to the most significant bit position than the trailing least significant zero bit position in an first input mask set to zero. In some embodiments, a second input mask is used as a writemask such that bit positions of the first input mask are not considered in the trailing least significant zero bit position calculation depending upon a corresponding bit position in the second input mask.
摘要翻译： KZBTZ的执行在第一输入掩码中找到尾随的最低有效零位位置，并将输出掩码设置为具有第一输入掩码的值，但是所有位位置都比接近最低有效位更靠近最高有效位位置第一个输入掩码中的零位位置设置为零。在一些实施例中，使用第二输入掩码作为写掩码，使得根据第二输入掩码中的相应位位置，在尾随最低有效零位位置计算中不考虑第一输入掩码的位位置。

40. 发明授权

US08447962B2 Gathering and scattering multiple data elements 有权
标题翻译：收集和散布多个数据元素
公开(公告)号：US08447962B2
公开(公告)日：2013-05-21
申请号：US12644440
申请日：2009-12-22
申请人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
发明人： Christopher J. Hughes , Yen-Kuang (Y. K.) Chen , Mayank Bomb , Jason W. Brandt , Mark J. Buxton , Mark J. Charney , Srinivas Chennupaty , Jesus Corbal , Martin G. Dixon , Milind B. Girkar , Jonathan C. Hall , Hideki (Saito) Ido , Peter Lachner , Gilbert Neiger , Chris J. Newburn , Rajesh S. Parthasarathy , Bret L. Toll , Robert Valentine , Jeffrey G. Wiedemeier
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/3865
摘要： According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.
摘要翻译：根据第一方面，可以通过以下方式来实现有效的数据传送操作：通过处理器设备解码指定在第一存储位置和第二存储位置之间的多个数据元素的传送操作的单个指令; 发出用于由处理器中的执行单元执行的单个指令; 在单个指令的执行期间检测异常的发生; 并且响应于异常，在传递异常之前将异常陷阱或中断传递给异常处理程序。

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