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31. 发明申请

US20060008013A1 Method and system for performing deblocking filtering 有权
标题翻译：执行去块滤波的方法和系统
公开(公告)号：US20060008013A1
公开(公告)日：2006-01-12
申请号：US10887132
申请日：2004-07-08
申请人： Oskar Pelc , Michael Zarubinsky , David Young
发明人： Oskar Pelc , Michael Zarubinsky , David Young
IPC分类号： H04B1/66 , G06K9/40
CPC分类号： H04N19/86 , H04N19/197 , H04N19/42 , H04N19/80
摘要： A system and method for filtering a frame, the method includes: (i) processing, by a processing unit executing instructions, at least one portion of a frame to provide at least one processed frame portion; (ii) performing, by a hardware filter, deblocking filtering of the at least one processed frame portion to provide at least one filtered frame portion; and (ii) storing the at least one filtered frame portion in a memory unit that is accessible by the processing unit; whereas the stage of processing is responsive to previously filtered frame portions. The system includes: (i) a processing unit, adapted to execute instructions such as to process at least one portion of a frame to provide at least one processed frame portion; (ii) a hardware filter, connected to the processing unit, adapted to deblocking filter the at least one processed frame portion to provide at least one filtered frame portion; and (iii) a memory unit, connected to the processing unit, adapted to store the at least one filtered frame portion; whereas the processing unit is adapted to process the at least one portion in response to previously filtered frame portions.
摘要翻译：一种用于过滤帧的系统和方法，所述方法包括：（i）通过执行指令的处理单元处理帧的至少一部分以提供至少一个经处理的帧部分; （ii）通过硬件滤波器执行所述至少一个经处理的帧部分的去块滤波以提供至少一个滤波的帧部分; 以及（ii）将所述至少一个滤波的帧部分存储在可由所述处理单元访问的存储器单元中; 而处理阶段响应于先前滤波的帧部分。该系统包括：（i）处理单元，适于执行诸如处理帧的至少一部分以提供至少一个已处理帧部分的指令; （ii）连接到所述处理单元的硬件滤波器，适于对所述至少一个经处理的帧部分进行去块滤波，以提供至少一个滤波的帧部分; 和（iii）连接到所述处理单元的适于存储所述至少一个滤波的帧部分的存储器单元; 而处理单元适于响应于先前滤波的帧部分来处理该至少一个部分。

32. 发明授权

US06683926B2 Gain controller with comparator offset compensation for circuit having in-phase and quadrature channels 有权
标题翻译：具有比较器偏移补偿的增益控制器，具有同相和正交通道的电路
公开(公告)号：US06683926B2
公开(公告)日：2004-01-27
申请号：US09740336
申请日：2000-12-18
申请人： Michael Zarubinsky , Ronen Paz , Vladimir Koifman
发明人： Michael Zarubinsky , Ronen Paz , Vladimir Koifman
IPC分类号： H04L2708
CPC分类号： H04L27/22 , H04L2027/0016 , H04L2027/0024
摘要： In a radio circuit (299) that forwards a signal pair (I,Q) by first (291, I) and second (292, Q) channels, by converting the signal pair (I,Q) from a digital form (ID, QD) to an analog form (IA, QA), a gain controller (200) monitors differences between the overall gains (GI, GQ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The gain controller (200) has digital comparators (221-224) at the inputs (281, 282) of the channels and analog comparators at the outputs (283, 284) of the channels. Intrinsic offsets of the analog comparators are determined and compensated by subtracting corresponding offsets from the digital comparators.
摘要翻译：在将信号对（I，Q）转换为第一（291，I）和第二（292，Q）信道的无线电电路（299）中，通过从数字形式（ID， QD）到模拟形式（IA，QA），增益控制器（200）监视通道中的总增益（GI，GQ）之间的差异，并通过将增益确定控制信号（W）反馈到一个来校正增益不平衡的渠道。增益控制器（200）在通道的输入（281,282）和通道的输出（283,284）处具有模拟比较器的数字比较器（221-224）。通过从数字比较器中减去相应的偏移来确定和补偿模拟比较器的固有偏移。

33. 发明授权

US06671336B1 Gain controller for circuit having in-phase and quadrature channels, and method 失效
标题翻译：具有同相和正交通道的电路的增益控制器及方法
公开(公告)号：US06671336B1
公开(公告)日：2003-12-30
申请号：US09572558
申请日：2000-05-16
申请人： Michael Zarubinsky , Ronen Paz , Vladimir Koifman
发明人： Michael Zarubinsky , Ronen Paz , Vladimir Koifman
IPC分类号： H04L2708
CPC分类号： H03D3/009 , H03C3/40 , H04L27/364 , H04L27/3809
摘要： In a radio circuit (299) that forwards a signal pair (I,Q) by a first channel (291, I) and by a second channel (292, Q), a gain controller (200) monitors differences between the overall gains (GI, GQ) in the channels and corrects a gain imbalance by feeding back a gain determining control signal (W) to one of the channels. The controller has first (221-224) and second (211-214) pluralities of single-bit comparators, operating at a high sampling rate, to monitor the signal pair at the channel inputs (281, 282) and at the channel outputs (283, 284), respectively, and to provide difference signals (&Dgr;X,&Dgr;Y) to an integrator (280) that calculates the gain control signal (W) at a decimated sampling rate (FR).
摘要翻译：在通过第一通道（291，I）和第二通道（292，Q）转发信号对（I，Q）的无线电电路（299）中，增益控制器（200）监视总增益（ GI，GQ），并且通过将增益确定控制信号（W）反馈到一个通道来校正增益不平衡。控制器具有以高采样率工作的第一（221-224）和第二（211-214）个单比特比较器，以监视信道输入（281,282）和信道输出（ 283,284），并且以提取的采样率（FR）计算增益控制信号（W）的积分器（280）提供差分信号（DeltaX，DeltaY）。

34. 发明授权

US06204783B1 Digital to analog convertor having a DC offset cancelling device and a method thereof 有权
标题翻译：具有DC偏移消除装置的数模转换器及其方法
公开(公告)号：US06204783B1
公开(公告)日：2001-03-20
申请号：US09273742
申请日：1999-03-22
申请人： Ronen Paz , Vladimir Koifman , Michael Zarubinsky
发明人： Ronen Paz , Vladimir Koifman , Michael Zarubinsky
IPC分类号： H03M106
CPC分类号： H03M1/0607 , H03M1/0682 , H03M1/66
摘要： A device and a method for canceling DC offset resulting from digital to analog conversion, wherein the device is coupled to a digital to analog comparator (i.e.—DAC), the device comprising of: an adder, coupled to the DAC, for adding a digital input signal IN(n) to a compensation signal CS(w−1), and sending the sum of IN(n) CS(w−1) to the DAC. An analog comparator, coupled to the DAC, for sampling the output signal OUT(t) of the DAC, for comparing the sampled signal ACS(n) to a first reference voltage VREF and for outputting a signal ACO(n) which represents the result of the comparison between ACS(n) and VREF. A DAC emulator, coupled to the DAC, for compensating for a time lapse between the appearance of a digital input signal IN(n) appearing at the input of the adder and an OUT(t), wherein OUT(t) resulted from IN(n). A digital comparator for receiving the output signals DES(n) of the DAC emulator, comparing DES(n) to a second reference value DREF and outputting a signal DCO(n) which represents the result of the comparison between DES(n) to DREF, and an offset calculation unit, coupled to the analog comparator and to the digital comparator for comparing ACO(n) and DCO(n) and sending to the adder, a compensation signal CS(n) which represents the result of the comparison between ACO(n) and DCO(n). The analog and digital comparator are driven by a clock signal which is not correlated to IN(n).
摘要翻译：一种用于消除由数模转换产生的DC偏移的装置和方法，其中所述装置耦合到数/模比较器（即，DAC），所述装置包括：耦合到DAC的加法器，用于将数字输入信号IN（n）到补偿信号CS（w-1），并将IN（n）CS（w-1）的和发送到DAC。耦合到DAC的模拟比较器，用于对DAC的输出信号OUT（t）进行采样，以将采样信号ACS（n）与第一参考电压VREF进行比较，并输出表示结果的信号ACO（n） ACS（n）和VREF之间的比较。 DAC模拟器，耦合到DAC，用于补偿出现在加法器输入端的数字输入信号IN（n）出现在OUT（t）之间的时间流逝，其中OUT（t）由IN n）。一种用于接收DAC仿真器的输出信号DES（n）的数字比较器，将DES（n）与第二参考值DREF进行比较，并输出表示DES（n）与DREF之间的比较结果的信号DCO（n），以及偏移计算单元，耦合到模拟比较器和数字比较器，用于比较ACO（n）和DCO（n），并向加法器发送表示ACO（n）和DCO（n）之间的比较结果的补偿信号CS （n）和DCO（n）。模拟和数字比较器由与IN（n）不相关的时钟信号驱动。

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