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31. 发明申请

US20070029604A1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
标题翻译：使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻
公开(公告)号：US20070029604A1
公开(公告)日：2007-02-08
申请号：US11546688
申请日：2006-10-12
申请人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
发明人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

32. 发明申请

US20060291282A1 Flash memory cell and methods for programming and erasing 有权
公开(公告)号：US20060291282A1
公开(公告)日：2006-12-28
申请号：US11511763
申请日：2006-08-29
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

33. 发明申请

US20060268593A1 Read-only memory array with dielectric breakdown programmability 审中-公开
标题翻译：具有介电击穿可编程性的只读存储阵列
公开(公告)号：US20060268593A1
公开(公告)日：2006-11-30
申请号：US11136981
申请日：2005-05-25
申请人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
发明人： Meng Ding , Zhizheng Liu , Yi He , Mark Randolph
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C2213/72 , H01L27/1021 , H01L27/112 , H01L27/11206 , H01L27/118
摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.
摘要翻译：根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。可编程ROM阵列还包括位于至少一个位线上的至少一个字线。可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。编程操作使存储单元作为二极管工作。可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

34. 发明授权

US07120063B1 Flash memory cell and methods for programming and erasing 有权
标题翻译：闪存单元和编程和擦除的方法
公开(公告)号：US07120063B1
公开(公告)日：2006-10-10
申请号：US10841850
申请日：2004-05-07
申请人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
发明人： Zhizheng Liu , Zengtao Liu , Yi He , Mark Randolph
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L29/66833
摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.
摘要翻译：提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池，其中栅极电压电位高于衬底电压电位。

35. 发明授权

US07058540B2 Method and system for accelerating power complementary cumulative distribution function measurements 失效
标题翻译：加速功率互补累积分布函数测量的方法和系统
公开(公告)号：US07058540B2
公开(公告)日：2006-06-06
申请号：US10737050
申请日：2003-12-15
申请人： Yi He , Gerald J. Ringel , Howard E. Hilton , Brian Barton
发明人： Yi He , Gerald J. Ringel , Howard E. Hilton , Brian Barton
IPC分类号： G06F15/00 , G06F7/38
CPC分类号： G06F17/18 , G01R21/133
摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.
摘要翻译：表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。直方图中每个直方图单元格的计数都存储在存储器中。每个浮点数作为存储器中对应的直方图bin的地址。然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并且从直方图数据导出CCDF曲线。将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

36. 发明申请

US20050143982A1 Method and system for accelerating power complementary cumulative distribution function measurements 失效
标题翻译：加速功率互补累积分布函数测量的方法和系统
公开(公告)号：US20050143982A1
公开(公告)日：2005-06-30
申请号：US10737050
申请日：2003-12-15
申请人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
发明人： Yi He , Gerald Ringel , Howard Hilton , Brian Barton
IPC分类号： G06F15/00 , G06F17/18
CPC分类号： G06F17/18 , G01R21/133
摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.
摘要翻译：表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。直方图中每个直方图单元格的计数都存储在存储器中。每个浮点数作为存储器中对应的直方图bin的地址。然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并从直方图数据中导出CCDF曲线。将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

37. 发明授权

US08975685B2 N-channel multi-time programmable memory devices 有权
标题翻译： N通道多时间可编程存储器件
公开(公告)号：US08975685B2
公开(公告)日：2015-03-10
申请号：US13600792
申请日：2012-08-31
申请人： Yi He , Xiang Lu , Albert Bergemont
发明人： Yi He , Xiang Lu , Albert Bergemont
IPC分类号： H01L29/788
CPC分类号： G11C16/0408 , G11C2216/10
摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.
摘要翻译：具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

38. 发明授权

US08710122B2 Halogen-free flame retardants for epoxy resin systems 有权
标题翻译：环氧树脂体系的无卤阻燃剂
公开(公告)号：US08710122B2
公开(公告)日：2014-04-29
申请号：US13128846
申请日：2009-11-24
申请人： Richard B. Ross , Yi He , Lisa S. Lim , Haohao Lin , Eumi Pyun
发明人： Richard B. Ross , Yi He , Lisa S. Lim , Haohao Lin , Eumi Pyun
IPC分类号： C08K5/521 , C08L63/00
CPC分类号： C08K5/521 , C08K3/32 , C08L63/00 , C09D5/18 , C09D163/00 , C08L2666/04
摘要： This disclosure relates to flame retardants that are useful for epoxy resin systems. Coating compositions and methods are provided the include an epoxy resin and a phosphate-containing flame retardant wherein the phosphate-containing flame retardant is selected from Group 1 metallic salts of a phosphate of a saccharide, Group 2 salts of a glycerophosphate, and Group 1 metallic salts of a polyphosphate. The provided flame retardants have low toxicity and are friendly to the environment.
摘要翻译：本发明涉及可用于环氧树脂体系的阻燃剂。提供了包括环氧树脂和含磷酸盐阻燃剂的涂料组合物和方法，其中含磷酸盐阻燃剂选自糖类磷酸盐的第1族金属盐，甘油磷酸盐的第2族盐和第1族金属多磷酸盐。所提供的阻燃剂具有低毒性，对环境友好。

39. 发明申请

US20130164709A1 SUBSTITUTED SACCHARIDE COMPOUNDS AND DENTAL COMPOSITIONS 有权
标题翻译：替代化合物和牙科成分
公开(公告)号：US20130164709A1
公开(公告)日：2013-06-27
申请号：US13813673
申请日：2011-08-19
申请人： Jie Yang , Sumita B. Mitra , Yi He , Brian A. Shukla , Naimul Karim , Afshin Falsafi , Richard B. Ross , Paul R. Klaiber , George W. Griesgraber
发明人： Jie Yang , Sumita B. Mitra , Yi He , Brian A. Shukla , Naimul Karim , Afshin Falsafi , Richard B. Ross , Paul R. Klaiber , George W. Griesgraber
IPC分类号： A61K6/00 , C07C271/16 , C07C233/20 , A61C7/30 , A61C5/10 , A61C13/271 , A61C7/28 , A61C8/00 , C07H15/12 , C07F9/09
CPC分类号： A61K6/0029 , A61K6/0023 , A61K6/083 , C07H13/12 , C08L33/24 , C08L33/10
摘要： Substituted saccharide compounds, dental compositions comprising substituted saccharide compounds, and methods of using dental compositions are described. In one embodiment, the substituted saccharide amide compound comprises a hydrophobic group and at least one free-radically polymerizable group with the proviso that the hydrophobic group is not bonded to the ethylenically unsaturated carbon atom of the free-radically polymerizable group. The hydrophobic group is typically bonded to a nitrogen atom of a saccharide amine residue or a carbonyl moiety of saccharide amide residue.
摘要翻译：描述了取代的糖类化合物，包含取代的糖类化合物的牙科组合物和使用牙科用组合物的方法。在一个实施方案中，取代的糖酰胺化合物包含疏水基团和至少一个可自由基聚合的基团，条件是疏水基团不与可自由基聚合基团的烯属不饱和碳原子键合。疏水基团通常键合到糖胺残基的氮原子或糖酰胺残基的羰基部分。

40. 发明授权

US08456868B2 Controller for a resonant switched-mode power converter 有权
标题翻译：谐振开关型功率转换器的控制器
公开(公告)号：US08456868B2
公开(公告)日：2013-06-04
申请号：US12771467
申请日：2010-04-30
申请人： Yi He , Tuck Meng Chan , Yong Siang Teo , Xiaowu Gong , Meng Kiat Jeoh
发明人： Yi He , Tuck Meng Chan , Yong Siang Teo , Xiaowu Gong , Meng Kiat Jeoh
IPC分类号： H02M3/335
CPC分类号： H02M3/3378 , H02M3/33592 , H02M2001/0058 , Y02B70/1433 , Y02B70/1475 , Y02B70/1491
摘要： An embodiment of the invention relates to an LLC power converter including a controller configured to regulate an output characteristic of the power converter by controlling a power converter switching frequency. In a first mode of operation, the controller turns off a secondary-side power switch earlier than a turn-off time of a primary-side power switch by a time difference that is controlled by a resistor coupled to an external circuit node. In a second mode of operation, the controller turns on a secondary-side power switch at substantially the same time as the primary-side power switch, and turns off the secondary-side power switch after a maximum on time that is a nonlinear function of a load current of the power converter. The nonlinear function is a substantially constant function of the load current for a value of the load current higher than a threshold value.
摘要翻译：本发明的实施例涉及一种LLC功率转换器，其包括被配置为通过控制功率转换器开关频率来调节功率转换器的输出特性的控制器。在第一操作模式中，控制器比次级侧电源开关早于初级侧电源开关的关断时间，该时间差由耦合到外部电路节点的电阻器控制。在第二操作模式中，控制器在与初级侧电源开关基本相同的时间接通次级侧电源开关，并且在作为非线性功能的最大导通时间之后关闭次级侧电源开关功率转换器的负载电流。对于高于阈值的负载电流的值，非线性函数是负载电流的基本上恒定的函数。

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