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31. 发明授权

US06667634B2 Multi-option setting device for a peripheral control chipset 有权
公开(公告)号：US06667634B2
公开(公告)日：2003-12-23
申请号：US10138021
申请日：2002-05-03
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： G06F738
CPC分类号： G06F13/4072
摘要： A multi-option setting device is provided for use in association with a connecting pin of a chipset for allowing user-selection from more than two setting options to set the chipset to perform one of more than two I/O functions through the associated connecting pin. The multi-option setting device includes voltage setting means for generating a user-specified input voltage; voltage comparison circuits for use to determine which pre-specified voltage range the user-specified input voltage lies; and latch circuits each for latching the corresponding output of the voltage comparison circuits. This allows the associated connecting pin to be optionally set to be used for a user-specified I/O function.

32. 发明授权

US06583365B2 Conductive pads layout for BGA packaging structure 有权
公开(公告)号：US06583365B2
公开(公告)日：2003-06-24
申请号：US10072213
申请日：2002-02-07
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： H05K116
CPC分类号： H01L23/49838 , H01L23/3128 , H01L23/50 , H01L23/5383 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/48237 , H01L2224/49111 , H01L2924/00014 , H01L2924/01014 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/30107 , H05K1/0216 , H05K1/181 , H05K2201/0792 , H05K2201/094 , H05K2201/10522 , H05K2201/10689 , H05K2203/049 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A conductive pad layout is implemented on a substrate for BGA packaging structure. The substrate has a top trace surface on which is attached a chip, and a bottom trace surface. The top trace surface includes a first contact pad, a second contact pad placed closer to the chip than the first contact pad, and a reference contact pad placed adjacent to the second contact pad. A first bonding wire connects the first contact pad to the chip, and second and third bonding wires of shorter length respectively connect the second contact pad and the reference contact pad to the chip. Thereby, critical signal can pass through the second bonding wire and second contact pad with reduced interference. A reference dummy ball pad is also placed adjacent to a ball pad corresponding to the second contact pad on a bottom trace surface of the substrate to reduce interference.

33. 发明授权

US06519708B1 Chip set comprising only graphic interface reference voltage pin 有权
标题翻译：芯片组仅包含图形接口参考电压引脚
公开(公告)号：US06519708B1
公开(公告)日：2003-02-11
申请号：US09436141
申请日：1999-11-09
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： G06F126
CPC分类号： G09G5/363
摘要： A chip set comprising only one graphic interface reference voltage pin. The chip set is installed onto a mother board to control accelerated graphics port. An example of the chip set comprises a corecircuit, a multiplexer, and a comparator. Only one graphic interference voltage lead is required to obtain the required internal reference voltage under different modes. Another example of the chip set connects to a multiplexer by the only graphic interface reference voltage pin. By coupling two pins of the mother board and the accelerated graphics accelerated port, the internal reference voltage can be controlled.
摘要翻译：一个只包含一个图形界面参考电压引脚的芯片组。芯片组安装在母板上，以控制加速图形端口。芯片组的示例包括核心电路，多路复用器和比较器。在不同的模式下，只需要一个图形干扰电压引线来获得所需的内部参考电压。芯片组的另一个例子是通过唯一的图形接口参考电压引脚连接到多路复用器。通过耦合母板的两个引脚和加速图形加速端口，可以控制内部参考电压。

34. 发明授权

US06446172B1 Method and system for controlling the memory access operation performed by a central processing unit in a computer system 有权
标题翻译：用于控制由计算机系统中的中央处理单元执行的存储器访问操作的方法和系统
公开(公告)号：US06446172B1
公开(公告)日：2002-09-03
申请号：US09335602
申请日：1999-06-18
申请人： Chia-Hsin Chen , Nai-Shung Chang
发明人： Chia-Hsin Chen , Nai-Shung Chang
IPC分类号： G06F1208
CPC分类号： G06F12/0859 , G06F13/161
摘要： A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner than the prior art. This memory access control method and system is characterized by, for each read request from the CPU, the prompt transfer of the corresponding internal read-request signal to the memory control unit, right after it is issued and without waiting until the CPU issues the L1 write-back signal of the current read request. If the current read request is a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back into the memory unit. This method and system can help reduce the period of waiting states by the CPU, thus increasing the overall memory access performance by the CPU and the overall system performance of the computer system.
摘要翻译：提供存储器访问控制方法和系统，用于在计算机系统上以比现有技术更有效的方式将中央处理单元（CPU）的存储器访问操作控制到存储器单元。这种存储器访问控制方法和系统的特征在于，对于来自CPU的每个读取请求，在相应的内部读取请求信号被发出之后立即将其传送到存储器控制单元，并且不等待直到CPU发出L1 当前读取请求的回写信号。如果当前读取请求是对高速缓存存储器的命中，则立即发出读停止信号以停止对存储器单元的当前读取操作，然后执行高速缓存回写操作以将高速缓存数据写回到存储单元该方法和系统可以帮助减少CPU等待状态的时间，从而提高CPU的整体内存访问性能以及计算机系统的整体系统性能。

35. 发明授权

US06229335B1 Input/output buffer capable of supporting a multiple of transmission logic buses 有权
标题翻译：能够支持多路传输逻辑总线的输入/输出缓冲器
公开(公告)号：US06229335B1
公开(公告)日：2001-05-08
申请号：US09417983
申请日：1999-10-13
申请人： Jincheng Huang , Nai-Shung Chang , Yuangtsang Liaw
发明人： Jincheng Huang , Nai-Shung Chang , Yuangtsang Liaw
IPC分类号： H03K1716
CPC分类号： H03K19/018585
摘要： An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.
摘要翻译：能够支持多种传输逻辑总线规格的输入/输出缓冲器。输入/输出缓冲器具有协调控制器，逻辑控制电路，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件。逻辑控制电路拾取微处理器型信号以确定所使用的微处理器的类型。根据微处理器类型，第一晶体管，第二晶体管，第一电阻元件和第二电阻元件的电导率被重新分配以适应微处理器的特定逻辑总线规范。因此，主电路板上的单个芯片组能够适应各种类型的微处理器。

36. 发明授权

US06173365B2 Cache memory system and method of a computer 失效
标题翻译：缓存内存系统和计算机方法
公开(公告)号：US06173365B2
公开(公告)日：2001-01-09
申请号：US09122454
申请日：1998-07-24
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： G06F1200
CPC分类号： G06F12/0802
摘要： A high-performance and cost-effective cache memory system is provided for use in conjunction with a high-speed computer system. The cache memory system is used on a computer system having a central processing unit (CPU) of the type having a back-off function that can be activated to temporarily halt the CPU when receiving a back-off signal. The cache memory system is capable of enabling the back-off signal in the event that the data read request signal from the CPU is determined to be a miss. During the back-off duration of the CPU, the requested data are moved from the primary memory unit to the cache memory module. This feature allows the overall performance of the computer system to be high even though a low-speed tag random-access memory (RAM) is used in the cache memory system, allowing the computer system to be highly cost-effective to use with high performance.
摘要翻译：提供了与高速计算机系统结合使用的高性能和具有成本效益的高速缓冲存储器系统。高速缓冲存储器系统用于具有这种类型的中央处理单元（CPU）的计算机系统，该中央处理单元（CPU）具有可被激活以在接收到退避信号时临时停止CPU的退避功能。高速缓冲存储器系统能够在来自CPU的数据读取请求信号被确定为错过的情况下启用退避信号。在CPU的退避时间期间，请求的数据从主存储器单元移动到高速缓冲存储器模块。即使在高速缓冲存储器系统中使用低速标签随机存取存储器（RAM），该功能也使得计算机系统的整体性能仍然很高，从而使计算机系统具有高性价比的高性能。

37. 发明授权

US6148398A Setting/driving circuit for use with an integrated circuit logic unit having multi-function pins 有权
标题翻译：用于具有多功能引脚的集成电路逻辑单元的设置/驱动电路
公开(公告)号：US6148398A
公开(公告)日：2000-11-14
申请号：US286230
申请日：1999-04-05
申请人： Wen-Ching Chang , Lin-Hung Chang , Nai-Shung Chang
发明人： Wen-Ching Chang , Lin-Hung Chang , Nai-Shung Chang
IPC分类号： G06F1/22 , G06F9/00
CPC分类号： G06F1/22
摘要： A setting/driving circuit is provided for use in conjunction with an IC logic unit, such as a CPU having one or more multi-function pins, to provide two or more sets of data, such as a set of parameter data and a set of control data, via the same multi-function pins to the CPU. The setting/driving circuit includes a tri-state buffer and a parameter setting unit composed of two resistors and a switch, such as a jumper. When the tri-state buffer is disabled, the parameter data set by the switch is transferred to the multi-function pin of the CPU. On the other hand, when the tri-state buffer is enabled, the input data to the input port of the tri-state buffer is transferred to the multi-function pin of the CPU. The tri-state buffer can be integrated within the chip set without having to increase the total number of pins on the chip set so that the layout complexity on the motherboard can be simpler and thus easier to assemble compared to the prior art. Therefore, the proposed setting/driving circuit is easier and more cost-effective to implement on a computer motherboard than the prior art.
摘要翻译：提供了一种设置/驱动电路，用于与诸如具有一个或多个多功能引脚的CPU的IC逻辑单元一起使用，以提供两组或更多组数据，例如一组参数数据和一组控制数据，通过相同的多功能引脚到CPU。设置/驱动电路包括三态缓冲器和由两个电阻器组成的参数设置单元和诸如跳线的开关。当三态缓冲器被禁用时，由开关设置的参数数据被传送到CPU的多功能引脚。另一方面，当启用三态缓冲器时，三态缓冲器的输入端口的输入数据被传送到CPU的多功能引脚。三态缓冲器可以集成在芯片组中，而不必增加芯片组上的引脚总数，使得与现有技术相比，主板上的布局复杂度可以更简单并且因此更容易组装。因此，在现有技术中，所提出的设置/驱动电路在计算机主板上的实现更容易，更具成本效益。

38. 发明授权

US07783905B2 Method for reducing power consumption of a computer system in the working state 有权
标题翻译：降低工作状态下计算机系统功耗的方法
公开(公告)号：US07783905B2
公开(公告)日：2010-08-24
申请号：US11423722
申请日：2006-06-13
申请人： Nai-Shung Chang , Chia-Hsing Yu
发明人： Nai-Shung Chang , Chia-Hsing Yu
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3225 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A method for reducing power consumption of a computer system in a working state is provided. The computer system comprises a processor, a memory and a chipset, and the processor is connected with the chipset through a processor bus. The method comprises classifying the power saving level of the computer system into a predetermined number of power saving modes, checking at least one power saving mode transition condition to determine whether to automatically raise the power saving mode of the computer system, and raising the power saving mode of the computer system by lowering a first voltage supply level of the chipset and a second voltage supply level of the memory and decreasing a first working frequency of the processor bus and a second working frequency of the memory. The power consumption of the computer system is further reduced in comparison with a normal working state when the power saving mode of the computer system is further raised.
摘要翻译：提供了一种降低处于工作状态的计算机系统的功耗的方法。计算机系统包括处理器，存储器和芯片组，并且处理器通过处理器总线与芯片组连接。该方法包括将计算机系统的省电水平分为预定数量的省电模式，检查至少一个省电模式转换条件，以确定是否自动提高计算机系统的省电模式，并提高节电通过降低芯片组的第一电压供应电平和存储器的第二电压供应电平并降低处理器总线的第一工作频率和存储器的第二工作频率来实现计算机系统的模式。当计算机系统的省电模式进一步提高时，与正常工作状态相比，计算机系统的功耗进一步降低。

39. 发明授权

US07047430B2 Method for saving chipset power consumption 有权
公开(公告)号：US07047430B2
公开(公告)日：2006-05-16
申请号：US09948850
申请日：2001-09-07
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： G06F1/26
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3287 , Y02D10/152 , Y02D10/171
摘要： A method of operating a chipset for saving power consumption is provided. Basic operating units, control units and input/output ports are used to simulate the operation inside the chipset. Any idling operating units are temporarily shut down, only to be activated again on demand. Ultimately, less power consumption is used and less heat is generated by the chipset.

40. 发明授权

US07024496B2 Operation method of input/output pad with monitoring ability 有权
标题翻译：具有监控能力的输入/输出板操作方法
公开(公告)号：US07024496B2
公开(公告)日：2006-04-04
申请号：US10930117
申请日：2004-08-30
申请人： Nai-Shung Chang
发明人： Nai-Shung Chang
IPC分类号： G06F3/00 , G06F13/00 , H03K19/003 , H03K17/16
CPC分类号： G06F13/4072
摘要： An I/O pad has a data transmitting circuit, a data monitoring control circuit, and a control selection circuit. The control selection circuit controls the data transmitting circuit. When it is enabled, data in the data transmitting circuit are exported to a receiving circuit. When it is disabled, data exportation stops. The data monitoring circuit receives signals of the data transmission circuit and export signals to the control selection circuit. The data monitoring circuit judges whether the data transmission is under a stable condition. If it is not, an unstable signal is exported to a first input end of the control selection circuit. A second input end of the control selection circuit receives an output enabling signal. When the data transmission is stable and the output enabling signal indicates a disable status, the control selection circuit disables the data transmitting circuit. Otherwise, the control selection circuit enables the data transmitting circuit.
摘要翻译： I / O焊盘具有数据发送电路，数据监视控制电路和控制选择电路。控制选择电路控制数据发送电路。当使能时，数据发送电路中的数据被输出到接收电路。禁用数据后，数据导出停止。数据监视电路接收数据传输电路的信号并将信号输出到控制选择电路。数据监视电路判断数据传输是否处于稳定状态。如果不是，则将不稳定的信号输出到控制选择电路的第一输入端。控制选择电路的第二输入端接收输出使能信号。当数据传输稳定并且输出使能信号指示禁止状态时，控制选择电路禁止数据发送电路。否则，控制选择电路使能数据发送电路。

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