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31. 发明申请

US20060246672A1 Method of forming a locally strained transistor 有权
标题翻译：形成局部应变晶体管的方法
公开(公告)号：US20060246672A1
公开(公告)日：2006-11-02
申请号：US11119522
申请日：2005-04-29
申请人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
发明人： Chien-Hao Chen , Donald Chao , Tze-Liang Lee
IPC分类号： H01L21/336 , H01L29/94 , H01L27/108 , H01L29/76 , H01L31/119
CPC分类号： H01L29/78 , H01L29/7843
摘要： A preferred embodiment of the invention provides a semiconductor fabrication method. An embodiment comprises forming a MOS device having sidewall spacers. A highly stressed layer is deposited over the device. The stress is selectively adjusted in that portion of the layer over the gate electrode and the sidewall spacers. Preferably, the stress layer over the gate electrode and over the sidewall spacers is adjusted from a first stress to a second stress, wherein the first stress is one of tensile and compressive, and the second stress is the other of tensile and compressive. Preferred embodiments selectively induce a suitable stress within PMOS and NMOS channel regions for improving their respective carrier mobility. Still other embodiments of the invention comprise a field effect transistor (FET) having a overlying stressed layer, the stressed layer being comprised of different stress regions.
摘要翻译：本发明的优选实施例提供半导体制造方法。一个实施例包括形成具有侧壁间隔物的MOS器件。高应力层沉积在器件上。在栅极电极和侧壁间隔物上的层的该部分中选择性地调节应力。优选地，栅极上方和侧壁间隔物上的应力层从第一应力调整到第二应力，其中第一应力是拉伸和压缩之一，第二应力是拉伸和压缩中的另一个。优选实施例在PMOS和NMOS沟道区域内选择性地诱发适当的应力，以改善它们各自的载流子迁移率。本发明的其它实施例包括具有上覆应力层的场效应晶体管（FET），所述应力层由不同的应力区域组成。

32. 发明申请

US20060099771A1 Selective nitride liner formation for shallow trench isolation 有权
标题翻译：用于浅沟槽隔离的选择性氮化物衬垫形成
公开(公告)号：US20060099771A1
公开(公告)日：2006-05-11
申请号：US10970090
申请日：2004-10-21
申请人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Vincent Chang , Ji-Yi Yang , Chia-Lin Chen , Tze-Liang Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method for forming a divot free nitride lined shallow trench isolation (STI) feature including providing a substrate including an STI trench extending through an uppermost hardmask layer into a thickness of the substrate exposing the substrate portions; selectively forming a first insulating layer lining the STI trench over said exposed substrate portions only; backfilling the STI trench with a second insulating layer; planarizing the second insulating layer; and, carrying out a wet etching process to remove the uppermost hardmask layer.
摘要翻译：一种用于形成无自由度的氮化物衬底浅沟槽隔离（STI）特征的方法，包括提供包括延伸穿过最上面的硬掩模层的STI沟槽的衬底，暴露衬底部分的衬底的厚度; 仅在所述暴露的衬底部分上选择性地形成衬在STI沟槽上的第一绝缘层; 用第二绝缘层回填STI槽; 平面化第二绝缘层; 并进行湿蚀刻处理以去除最上面的硬掩模层。

33. 发明申请

US20060094194A1 Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology 审中-公开
标题翻译：用于低于90NM CMOS技术的低温高应力氮化膜的高级一次性间隔工艺
公开(公告)号：US20060094194A1
公开(公告)日：2006-05-04
申请号：US10982115
申请日：2004-11-04
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/2658 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprises providing a gate electrode having exposed side walls formed in a substrate, forming dummy spacers on the gate electrode exposed side walls, performing a first implant to form source and drain implants, forming a capping layer over the gate electrode, the dummy sidewall spacers, and the source and drain, performing a first anneal, and removing the capping layer and the dummy sidewall spacers.
摘要翻译：一种形成半导体器件的方法包括提供栅电极，其具有形成在衬底中的暴露的侧壁，在栅极电极暴露的侧壁上形成虚设间隔物，执行第一注入以形成源极和漏极注入，在栅极上形成覆盖层电极，虚拟侧壁间隔物以及源极和漏极，执行第一退火，以及去除覆盖层和虚设侧壁间隔物。

34. 发明申请

US20050136583A1 Advanced strained-channel technique to improve CMOS performance 审中-公开
标题翻译：先进的应变通道技术，以提高CMOS性能
公开(公告)号：US20050136583A1
公开(公告)日：2005-06-23
申请号：US10744746
申请日：2003-12-23
申请人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/8238 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823842
摘要： A method of improving CMOS device performance, comprising the following steps. A structure having a gate electrode formed thereover and a channel formed thereunder is provided. The gate electrode having an initial lower width and an initial upper width. A capping layer having a tensile stress is formed over the structure and the gate electrode. The gate electrode is annealed to achieve tensile stress in the channel.
摘要翻译：一种提高CMOS器件性能的方法，包括以下步骤。提供了具有形成在其上的栅电极和在其下形成的沟道的结构。栅电极具有初始下宽度和初始上宽度。在结构和栅电极上形成具有拉伸应力的覆盖层。栅电极退火以在通道中实现拉伸应力。

35. 发明授权

US07316970B2 Method for forming high selectivity protection layer on semiconductor device 有权
标题翻译：在半导体器件上形成高选择性保护层的方法
公开(公告)号：US07316970B2
公开(公告)日：2008-01-08
申请号：US10892014
申请日：2004-07-14
申请人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chien-Hao Chen , Ju-Wang Hsu , Chia-Lin Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/425
CPC分类号： H01L21/31111 , H01L21/823481 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： A method for forming a resist protect layer on a semiconductor substrate includes the following steps. An isolation structure is formed on the semiconductor substrate. An original nitride layer having a substantial etch selectivity to the isolation structure is formed over the semiconductor substrate. A photoresist mask is formed for partially covering the original nitride layer. A wet etching is performed to remove the original nitride layer uncovered by the photoresist mask in such a way without causing substantial damage to the isolation structure. As such, the original nitride layer covered by the photoresist mask constitutes the resist protect layer.
摘要翻译：在半导体衬底上形成抗蚀剂保护层的方法包括以下步骤。在半导体衬底上形成隔离结构。在半导体衬底上形成对隔离结构具有实质蚀刻选择性的原始氮化物层。形成光致抗蚀剂掩模以部分覆盖原始氮化物层。执行湿蚀刻以以这样的方式去除由光致抗蚀剂掩模未覆盖的原始氮化物层，而不会对隔离结构造成实质损坏。因此，由光致抗蚀剂掩模覆盖的原始氮化物层构成抗蚀剂保护层。

36. 发明申请

US20070287240A1 Advanced forming method and structure of local mechanical strained transistor 有权
标题翻译：局部机械应变晶体管的先进成形方法和结构
公开(公告)号：US20070287240A1
公开(公告)日：2007-12-13
申请号：US11450210
申请日：2006-06-09
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/823807 , H01L27/0922 , H01L29/16 , H01L29/161 , H01L29/7833
摘要： Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
摘要翻译：本发明的实施例提供半导体制造方法和应变晶体管的结构。一种方法包括在MOS晶体管上形成应力层。在栅电极上选择性地蚀刻应力层，从而影响MOSFET沟道区内的应变条件。 NMOS晶体管可以具有拉伸应力层，并且PMOS晶体管可以具有压应力层。

37. 发明授权

US07164163B2 Strained transistor with hybrid-strain inducing layer 有权
标题翻译：具有杂化应变诱导层的应变晶体管
公开(公告)号：US07164163B2
公开(公告)日：2007-01-16
申请号：US11062723
申请日：2005-02-22
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/4983 , H01L29/66628 , H01L29/66636 , H01L29/7843
摘要： A semiconductor device having a hybrid-strained layer and a method of forming the same are discussed. The semiconductor device comprises: a gate dielectric over a substrate; a gate electrode over the gate dielectric; an optional pair of spacers along the sidewalls of the gate dielectric and the gate electrode; a source/drain region substantially aligned with an edge of the gate electrode; and a strained layer over the source/drain region, gate electrode, and spacers wherein the strained layer has a first portion and a second portion. The first portion of the strained layer is substantially over the source/drain region and has a first inherent strain. The second portion of the strained layer has at least a portion substantially over the gate electrode and the spacers and has a second inherent strain of the opposite type of the first strain.
摘要翻译：讨论了具有混合应变层的半导体器件及其形成方法。半导体器件包括：衬底上的栅极电介质; 位于栅极电介质上的栅电极; 沿着栅极电介质和栅电极的侧壁的可选的一对间隔物; 源极/漏极区域，其基本上与栅电极的边缘对齐; 以及源极/漏极区域上的应变层，栅电极和间隔物，其中应变层具有第一部分和第二部分。应变层的第一部分基本上在源极/漏极区域之上并且具有第一固有应变。应变层的第二部分具有基本上在栅电极和间隔物上的至少一部分，并且具有相反类型的第一应变的第二固有应变。

38. 发明申请

US20060267106A1 Novel semiconductor device with improved channel strain effect 审中-公开
标题翻译：新型半导体器件具有改善的通道应变效应
公开(公告)号：US20060267106A1
公开(公告)日：2006-11-30
申请号：US11137495
申请日：2005-05-26
申请人： Donald Chao , Chien-Hao Chen , Ling-Yen Yeh , Tze-Liang Lee , Shih-Chang Chen
发明人： Donald Chao , Chien-Hao Chen , Ling-Yen Yeh , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/772
CPC分类号： H01L29/6656 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A semiconductor device includes a substrate, a gate structure over the substrate, a first sidewall spacer on a sidewall of the gate structure, a first diffusion region in the substrate and adjacent to the gate structure, the first sidewall spacer and the first diffusion region being on one side of the gate structure, and a first conductive layer in the first diffusion region, the first conductive layer being spaced apart from the first sidewall spacer.
摘要翻译：半导体器件包括衬底，衬底上的栅极结构，栅极结构的侧壁上的第一侧壁间隔物，衬底中的第一扩散区域和栅极结构附近，第一侧壁间隔物和第一扩散区域是在所述栅极结构的一侧，以及所述第一扩散区域中的第一导电层，所述第一导电层与所述第一侧壁间隔物间隔开。

39. 发明申请

US20060049470A1 Double layer polysilicon gate electrode 审中-公开
标题翻译：双层多晶硅栅电极
公开(公告)号：US20060049470A1
公开(公告)日：2006-03-09
申请号：US10936271
申请日：2004-09-07
申请人： Chia-Lin Chen , Ming-Jie Huang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen
发明人： Chia-Lin Chen , Ming-Jie Huang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L29/76
CPC分类号： H01L29/4925 , H01L21/28035 , H01L29/665
摘要： A method for forming a microelectronic product and the microelectronic product resulting from the method both employ a bilayer gate electrode. The bilayer gate electrode employs: (1) a first layer formed of a random oriented polycrystalline silicon material; and (2) a second layer laminated to the first layer and formed of a columnar oriented polycrystalline silicon material. The gate electrode provides enhanced performance to a semiconductor device within which it is formed.
摘要翻译：形成微电子产物的方法和由该方法得到的微电子产物都采用双层栅电极。双层栅极采用：（1）由随机取向的多晶硅材料形成的第一层; 和（2）层压到第一层并由柱状取向的多晶硅材料形成的第二层。栅电极为其形成的半导体器件提供增强的性能。

40. 发明申请

US20110175161A1 Advanced Forming Method and Structure of Local Mechanical Strained Transistor 审中-公开
标题翻译：局部机械应变晶体管的先进成形方法和结构
公开(公告)号：US20110175161A1
公开(公告)日：2011-07-21
申请号：US13077641
申请日：2011-03-31
申请人： Chien-Hao Chen , Tze-Liang Lee
发明人： Chien-Hao Chen , Tze-Liang Lee
IPC分类号： H01L29/78
CPC分类号： H01L29/7843 , H01L21/28123 , H01L21/823807 , H01L27/0922 , H01L29/16 , H01L29/161 , H01L29/7833
摘要： Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.
摘要翻译：本发明的实施例提供半导体制造方法和应变晶体管的结构。一种方法包括在MOS晶体管上形成应力层。在栅电极上选择性地蚀刻应力层，从而影响MOSFET沟道区内的应变条件。 NMOS晶体管可以具有拉伸应力层，并且PMOS晶体管可以具有压应力层。

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