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31. 发明授权

US06171906B2 Method of forming sharp beak of poly to improve erase speed in split gate flash 有权
标题翻译：形成尖锐喙的方法，以提高分流闸闪光中的擦除速度
公开(公告)号：US06171906B2
公开(公告)日：2001-01-09
申请号：US09379227
申请日：1999-08-23
申请人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Chuang-Ke Yeh , Di-Son Kuo
发明人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Chuang-Ke Yeh , Di-Son Kuo
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.
摘要翻译：提供了一种用于形成具有尖锐尖峰的分裂栅极闪存单元的方法，其大大改善了单元的编程擦除速度。通过对第一多晶硅层的氧化后形成的多氧化物进行额外且明智的湿法蚀刻，形成尖锐的喙。额外的氧化物浸渍导致周围地去除多氧化物，从而沿着浮动栅极的边缘形成重入腔。再入口的喙使得在后续工艺步骤中不会损坏，特别适用于小于0.35微米的电池尺寸。

32. 发明授权

US6124609A Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio 有权
标题翻译：具有埋地源的分流式闪存，以收缩电池尺寸并增加耦合比
公开(公告)号：US6124609A
公开(公告)日：2000-09-26
申请号：US439369
申请日：1999-11-15
申请人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
发明人： Chia-Ta Hsieh , Jenn Tsao , Di-Son Kuo , Yai-Fen Lin , Hung-Cheng Sung
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is provided for forming a split-gate flash memory cell having reduced size, partially buried source line, increased source coupling ratio, improved programmability, and overall enhanced performance. A split-gate cell is also provided with reduced size and improved performance. The source line is formed in a trench in the substrate over the source region. The trench walls provide increased source coupling and the absence of gate bird's beak with the trench together shrink the cell size. Programmability is also enhanced through more favorable hot electron injection though intergate oxide between the floating gate and the control gate.
摘要翻译：提供了一种用于形成具有减小的尺寸，部分埋入的源极线，增加的源耦合比，改进的可编程性和整体增强性能的分裂栅极快闪存储器单元的方法。分裂门电池还具有减小的尺寸和改进的性能。源极线形成在源极区域上的衬底中的沟槽中。沟槽壁提供增加的源耦合，并且没有门鸟的喙与沟槽一起收缩细胞尺寸。通过浮动栅极和控制栅极之间的隔间氧化物，通过更有利的热电子注入也可以提高可编程性。

33. 发明授权

US5972753A Method of self-align cell edge implant to reduce leakage current and improve program speed in split-gate flash 失效
标题翻译：自对准单元边缘注入的方法，以减少漏电流并提高分闸门闪存中的编程速度
公开(公告)号：US5972753A
公开(公告)日：1999-10-26
申请号：US984842
申请日：1997-12-04
申请人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
发明人： Yai-Fen Lin , Hung-Cheng Sung , Chia-Ta Hsieh , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for fabricating a self-aligned edge implanted split-gate flash memory comprising a semiconductor substrate of a first conductivity type having separated first and second regions of a second conductivity type formed therein, the first and second regions defining a substrate channel region therebetween; a floating gate separated from a doped region in the substrate by an oxide layer; a control gate partially overlying and separated by an insulator from said floating gate; said floating gate having thin portions and thick portions; and said thin portions of said floating gate overlying twice doped regions said semiconductor substrate to reduce surface leakage current and improve program speed of the memory cell.
摘要翻译：提供了一种用于制造自对准边缘注入分裂栅极闪存的方法，该闪存包括形成有分离的第二和第二区域的第一导电类型的半导体衬底，第一和第二区域限定衬底沟道区域之间; 通过氧化物层与衬底中的掺杂区域分离的浮置栅极; 由所述浮动栅极部分地由绝缘体覆盖并分离的控制栅极; 所述浮栅具有薄部分和厚部分; 并且所述浮动栅极的所述薄部分覆盖两个掺杂区域的所述半导体衬底，以减少表面泄漏电流并提高存储器单元的编程速度。

34. 发明授权

US5940706A Process for preventing misalignment in split-gate flash memory cell 失效
标题翻译：用于防止分闸式闪存单元中的未对准的过程
公开(公告)号：US5940706A
公开(公告)日：1999-08-17
申请号：US988764
申请日：1997-12-11
申请人： Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
发明人： Hung-Cheng Sung , Di-Son Kuo , Yai-Fen Lin , Chia-Ta Hsieh
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A select transistor for flash memory cells is made by the following steps. Over the blanket second dielectric layer, and an oxynitride layer form a channel mask for patterning the drain and floating gate. Etch the oxynitride layer through the mask to form a channel alignment mask down to a silicon nitride layer with a drain region opening and a floating gate opening. Etch the floating gate opening through the second dielectric layer. Form a polyoxide region in the floating gate layer at the bottom of the floating gate opening by reacting the exposed portion of the floating gate layer with a reactant. Form a drain region in the substrate. Etch away the oxynitride layer and the silicon nitride layer. Pattern the floating gate electrode by etching away the floating gate layer except below the polyoxide region. Form an interelectrode dielectric layer and a second gate electrode layer over the drain region and a portion of the polyoxide region. Form a source region in the substrate self-aligned with the polyoxide region.
摘要翻译：用于闪存单元的选择晶体管通过以下步骤进行。在整个第二介电层上，并且氧氮化物层形成用于图案化漏极和浮置栅极的沟道掩模。通过掩模蚀刻氧氮化物层以形成通道对准掩模，直到具有漏极区域开口和浮动开口的氮化硅层。通过第二介电层蚀刻浮动开口。通过使浮栅的暴露部分与反应物反应，在浮动栅极开口底部的浮栅中形成多氧化物区域。在衬底中形成漏区。蚀刻掉氧氮化物层和氮化硅层。通过蚀刻除了多晶氧化物区域之外的浮栅层来对浮栅电极进行图案化。在漏极区域和一部分多氧化物区域上形成电极间电介质层和第二栅电极层。在与氧化物区域自对准的衬底中形成源区。

35. 发明授权

US5879992A Method of fabricating step poly to improve program speed in split gate flash 失效
标题翻译：制造步骤聚合物以提高分流栅闪光中程序速度的方法
公开(公告)号：US5879992A
公开(公告)日：1999-03-09
申请号：US115719
申请日：1998-07-15
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-Ke Yeh , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/8427
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.
摘要翻译：提供了一种用于形成分支栅极快闪存储器单元的方法，其具有支撑不同厚度的多晶硅氧化物的台阶聚合物，以改善电池的全部性能。多晶氧化物形成在第一多晶硅层的部分上，该第一多晶硅层又被部分蚀刻以形成邻近聚氧化物下面的浮动栅极的侧壁的台阶。接着在步骤poly上由热的温度氧化物形成间隔物。然后形成间极氧氮化物，并且控制栅极被图案化与浮置栅极与介入的多晶硅氧化物重叠。步进多晶硅和间隔件在控制栅极和浮动栅极之间形成适当的距离，同时保持多晶硅尖端和控制栅极之间的距离不变，使得控制栅极和浮动栅极之间以及浮动栅极和浮动栅极之间的适当耦合实现了衬底，从而改进了具有阶梯聚光的分离栅极闪存的全部性能。

36. 发明授权

US5858840A Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash 失效
标题翻译：通过氮注入形成聚合尖锐尖嘴的方法，以提高分流栅闪光的擦除速度
公开(公告)号：US5858840A
公开(公告)日：1999-01-12
申请号：US995341
申请日：1997-12-22
申请人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Di-Son Kuo
发明人： Chia-Ta Hsieh , Hung-Cheng Sung , Yai-Fen Lin , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/82
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A method is provided for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.
摘要翻译：提供了一种用于形成短而尖锐的门鸟喙的方法，以便增加分闸式闪存单元的擦除速度。这是通过将氮离子注入到电池的第一多晶硅层中并将其从要形成浮栅的区域中去除来实现的。然后，当多晶硅层被氧化形成聚氧化物时，没有氮离子的浮栅区域比仍然具有氮离子的周围区域更快地氧化。因此，形成在多氧化物边缘的鸟嘴形状比现有技术中发现的具有更小的形状。这导致存储单元的擦除速度的增加。

37. 发明授权

US07417278B2 Method to increase coupling ratio of source to floating gate in split-gate flash 有权
标题翻译：提高分流栅闪光时源极与浮栅耦合比的方法
公开(公告)号：US07417278B2
公开(公告)日：2008-08-26
申请号：US11122726
申请日：2005-05-05
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7885
摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.
摘要翻译：提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。控制栅极通过中间多晶硅氧化物形成在浮动栅上。浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

38. 发明授权

US06573555B1 Source side injection programming and tip erasing P-channel split gate flash memory cell 有权
标题翻译：源端注入编程和引脚擦除P沟道分离栅极闪存单元
公开(公告)号：US06573555B1
公开(公告)日：2003-06-03
申请号：US09587464
申请日：2000-06-05
申请人： Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Chia-Ta Hsieh
发明人： Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Chia-Ta Hsieh
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.
摘要翻译：分裂门P沟道快闪存储单元以及形成分离栅极P沟道闪存单元的方法，其避免高擦除电压，编程期间的反向隧穿，漏极干扰和过度擦除问题，并且允许缩小单元尺寸。控制门具有与侧壁相交以形成锋利边缘的凹顶表面。通过从通道进入浮动栅极的热电子注入，用电子对浮动栅极充电来对单元进行编程。使用Fowler-Nordheim隧道将多余的电子从浮动栅极放电到控制栅中来消除电池。在凹顶表面和浮动栅极的相交处的尖锐边缘在控制栅极和浮动栅极之间产生高电场，以在浮动栅极和控制栅极之间仅具有适度的电压差来实现Fowler-Nordheim隧道。 P沟道闪速存储单元对于产生热电子具有较高的冲击电离强度，使得源极和漏极结之间的距离和浮置栅极的长度可以保持较小，从而允许闪存单元的尺寸缩小。

39. 发明授权

US06538277B2 Split-gate flash cell 有权
标题翻译：分离式闪存单元
公开(公告)号：US06538277B2
公开(公告)日：2003-03-25
申请号：US09920601
申请日：2001-08-02
申请人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
发明人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76895 , H01L21/76897 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.
摘要翻译：公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

40. 发明授权

US06534821B2 Structure with protruding source in split-gate flash 有权
公开(公告)号：US06534821B2
公开(公告)日：2003-03-18
申请号：US09927071
申请日：2001-08-10
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Hung-Cheng Sung , Chuang-ke Yeh , Wen-Ting Chu , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell. The vertical orientation of the source structure and the floating gate and the self-alignment of the spacer control gate to the floating gate together makes it possible to reduce the memory cell substantially.

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