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31. 发明申请

US20080186780A1 Non-volatile memory with improved erasing operation 有权
标题翻译：非易失性存储器，具有改进的擦除操作
公开(公告)号：US20080186780A1
公开(公告)日：2008-08-07
申请号：US11703916
申请日：2007-02-07
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/14
CPC分类号： G11C11/5635 , G11C16/107 , G11C16/16 , G11C16/3459 , G11C2211/5621
摘要： A method for performing an erase operation is disclosed in a non-volatile memory having a plurality of memory cells. At least one memory cell is programmed having a threshold voltage level in a first region before programming, and after programming the memory cell has a threshold voltage level in a second region, wherein the second region is higher in threshold voltage than the fist region. The erasing operation implements a programming of memory bits that can inject negative charge carriers or electrons into a memory cell instead of using the conventional technique of injecting hot holes into the memory cell. This can avoid room temperature drift and charge loss caused by hot hole injection.
摘要翻译：在具有多个存储单元的非易失性存储器中公开了一种用于执行擦除操作的方法。至少一个存储器单元被编程为在编程之前具有第一区域中的阈值电压电平，并且在编程之后，存储器单元在第二区域中具有阈值电压电平，其中第二区域的阈值电压高于第一区域。擦除操作实现了可以将负电荷载流子或电子注入到存储单元中的存储器位的编程，而不是使用将热空穴注入存储单元的常规技术。这可以避免热空穴注入引起的室温漂移和电荷损失。

32. 发明申请

US20080094891A1 Parallel Threshold Voltage Margin Search for MLC Memory Application 有权
标题翻译：并行阈值电压裕度搜索MLC内存应用程序
公开(公告)号：US20080094891A1
公开(公告)日：2008-04-24
申请号：US11551974
申请日：2006-10-23
申请人： Wen-Chiao Ho , Chin-Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C7/00 , G11C29/00
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译：用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。

33. 发明授权

US08723559B2 Dynamic driver circuit 有权
标题翻译：动态驱动电路
公开(公告)号：US08723559B2
公开(公告)日：2014-05-13
申请号：US13603815
申请日：2012-09-05
申请人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03B1/00 , H03K3/00
CPC分类号： G11C8/08 , G11C16/08
摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.
摘要翻译：可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流源电压，克服第一静电流。此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压。

34. 发明申请

US20140062543A1 DYNAMIC DRIVER CIRCUIT 有权
标题翻译：动力驱动电路
公开(公告)号：US20140062543A1
公开(公告)日：2014-03-06
申请号：US13603815
申请日：2012-09-05
申请人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Chang-Ting Chen , Chin-Hung Chang , Shang-Chi Yang , Kuan-Ming Lu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03K3/00
CPC分类号： G11C8/08 , G11C16/08
摘要： A circuit usable as a word line driver includes a driver that switches in response to a voltage on a control node, and a circuit supplying a voltage to the control node. The circuit that applies a voltage to control node provides a first static current tending to pull the control node up to a first source voltage, and provides a fighting current pulse in response to a signal selecting the driver to pull the control node down to a second source voltage, overcoming the first static current. In addition, a circuit provides a pull-up boost current on a transition of the signal selecting the driver that turns off the fighting current, and applies a boosting current pulse to the control node to assist pulling the control node quickly to the first source voltage.
摘要翻译：可用作字线驱动器的电路包括响应于控制节点上的电压而切换的驱动器，以及向控制节点提供电压的电路。向控制节点施加电压的电路提供趋向于将控制节点拉至第一源电压的第一静态电流，并且响应于选择驱动器的信号提供战斗电流脉冲以将控制节点向下拉到第二静态电流源电压，克服第一静电流。此外，电路在选择驱动器的信号转变时提供上拉升压电流，该信号使关闭电流消失，并且向控制节点施加升压电流脉冲，以帮助快速将控制节点拉到第一源电压。

35. 发明授权

US08223559B2 Method of programming a memory 有权
标题翻译：编程存储器的方法
公开(公告)号：US08223559B2
公开(公告)日：2012-07-17
申请号：US12970222
申请日：2010-12-16
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/12 , G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.
摘要翻译：一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。在编程方法的实施例中，对应的数据分别输入到数据缓冲器。对应于第n阶段的数据被编程到目标多级单元中。修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理根据第n个编程验证电压。重复上述步骤直到n等于最大值，n为正整数。

36. 发明授权

US07755945B2 Page buffer and method of programming and reading a memory 有权
标题翻译：页面缓冲区和编程和读取存储器的方法
公开(公告)号：US07755945B2
公开(公告)日：2010-07-13
申请号：US12182245
申请日：2008-07-30
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5646 , G11C2216/14
摘要： A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.
摘要翻译：提供了一种页面缓冲器和编程和读取存储器的方法。页面缓冲器包括第一锁存器，第二锁存器，数据改变单元和程序控制单元。第一锁存器包括用于加载下页和上页的数据的第一终端。第二锁存器包括用于存储来自第一锁存器的下页数据和上页数据的第一终端。数据改变单元耦合到第一锁存器的第二端子，用于将第一锁存器的第二端子的电压改变到低电平。程序控制单元耦合到第二锁存器和单元的第一端子，并且由第一锁存器的第一端子的电压控制，以分别将下页数据和上部页面的数据编程到目标单元。

37. 发明申请

US20080123406A1 Dynamic Program and Read Adjustment for Multi-Level Cell Memory Array 有权
标题翻译：多级单元存储器阵列的动态程序和读取调整
公开(公告)号：US20080123406A1
公开(公告)日：2008-05-29
申请号：US11555849
申请日：2006-11-02
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C2211/5621
摘要： A method for operating a multi-level cell (“MLC”) memory array of an integrated circuit (“IC”) programs first data into a first plurality of MLCs in the MLC memory array at a first programming level. Threshold voltages for the first plurality of MLCs are sensed, and an adjust code is set according to the threshold voltages. Second data is programmed into a second plurality of MLCs in the MLC memory array at a second programming level, the second plurality of MLCs having a program-verify value set according to the adjust code. In a further embodiment, a reference voltage for reading the second plurality of MLCs is set according to the adjust code.
摘要翻译：用于操作集成电路（“IC”）的多级单元（“MLC”）存储器阵列的方法在第一编程级将第一数据编程到MLC存储器阵列中的第一多个MLC中。感测第一多个MLC的阈值电压，并且根据阈值电压设置调整代码。第二数据在第二编程级别被编程到MLC存储器阵列中的第二多个MLC中，第二多个MLC具有根据调整代码设置的程序验证值。在另一实施例中，根据调整代码来设置用于读取第二多个MLC的参考电压。

38. 发明申请

US20130242665A1 Method and Apparatus for Shortened Erase Operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US20130242665A1
公开(公告)日：2013-09-19
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

39. 发明申请

US20110085380A1 Method of Programming a Memory 有权
标题翻译：存储器编程方法
公开(公告)号：US20110085380A1
公开(公告)日：2011-04-14
申请号：US12970222
申请日：2010-12-16
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.
摘要翻译：一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。在编程方法的实施例中，对应的数据分别输入到数据缓冲器。对应于第n阶段的数据被编程到目标多级单元中。修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理根据第n个编程验证电压。重复上述步骤直到n等于最大值，n为正整数。

40. 发明申请

US20100054045A1 Memory and Reading Method Thereof 有权
标题翻译：记忆和阅读方法
公开(公告)号：US20100054045A1
公开(公告)日：2010-03-04
申请号：US12204009
申请日：2008-09-04
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C16/24 , G11C16/26
摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.
摘要翻译：存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。源极线耦合到目标存储器单元的第一端子。位线耦合到目标存储器单元的第二端子。读取控制电路用于选择性地向源极线施加工作电压。

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