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31. 发明申请

US20110127673A1 WIRING STRUCTURE AND METHOD 审中-公开
标题翻译：接线结构和方法
公开(公告)号：US20110127673A1
公开(公告)日：2011-06-02
申请号：US12628481
申请日：2009-12-01
申请人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76834 , H01L21/76883 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is an improved integrated circuit wiring structure configured to prevent migration of wiring metal ions (e.g., copper (Cu+) ions in the case of a copper interconnect scheme) onto the surface of an interlayer dielectric material at an interface between the interlayer dielectric material and an insulating cap layer. Specifically, the top surfaces of wires and the top surface of a dielectric layer within which the wires sit are not co-planar. Thus, the interfaces between the wires and an insulating cap layer and between the dielectric layer and the same insulating cap layer are also not co-planar. Such a configuration physically prevents migration of wiring metal ions from the top surface of the wires onto the top surface of the dielectric layer at the interface between the dielectric layer and cap layer and, thereby prevents time dependent dielectric breakdown (TDDB) and eventual device failure. Also disclosed herein are embodiments of a method of a forming such an integrated circuit wiring structure.
摘要翻译：公开了一种改进的集成电路布线结构，其被配置为防止布线金属离子（例如在铜互连方案的情况下的铜（Cu +）离子）迁移到层间电介质材料的表面上，在层间电介质材料和绝缘盖层。具体地，电线的顶表面和电线所在的电介质层的顶表面不是共面的。因此，电线和绝缘帽层之间以及电介质层和相同绝缘帽层之间的界面也不是共面的。这种配置物理上防止布线金属离子从电介质顶表面在介电层和盖层之间的界面处迁移到电介质层的顶表面上，从而防止时间依赖的介质击穿（TDDB）和最终的器件故障。本文还公开了形成这种集成电路布线结构的方法的实施例。

32. 发明授权

US07915158B2 Method for forming an on-chip high frequency electro-static discharge device 有权
标题翻译：用于形成片上高频静电放电装置的方法
公开(公告)号：US07915158B2
公开(公告)日：2011-03-29
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属层布线的晶片。该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到在第二介电层中分别有一个以上的电极。多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

33. 发明申请

US20100320571A1 BIPOLAR TRANSISTOR STRUCTURE AND METHOD INCLUDING EMITTER-BASE INTERFACE IMPURITY 有权
标题翻译：双极晶体管结构和方法，其中包括发射极基底界面强度
公开(公告)号：US20100320571A1
公开(公告)日：2010-12-23
申请号：US12488899
申请日：2009-06-22
申请人： John J. Benoit , Mattias E. Dahlstrom , Mark D. Dupuis , Peter B. Gray , Anthony K. Stamper
发明人： John J. Benoit , Mattias E. Dahlstrom , Mark D. Dupuis , Peter B. Gray , Anthony K. Stamper
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/732 , H01L29/0821 , H01L29/0826 , H01L29/167 , H01L29/207 , H01L29/227 , H01L29/34 , H01L29/66272
摘要： A bipolar transistor structure and a method for fabricating the bipolar transistor structure include: (1) a collector structure located at least in-part within a semiconductor substrate; (2) a base structure contacting the collector structure; and (3) an emitter structure contacting the base structure. The interface of the emitter structure and the base structure includes an oxygen impurity and at least one impurity selected from the group consisting of a fluorine impurity and a carbon impurity, to enhance performance of a bipolar transistor within the bipolar transistor structure. The impurities may be introduced into the interface by plasma etch treatment, or alternatively a thermal treatment followed by an anhydrous ammonia and hydrogen fluoride treatment, of a base material from which is comprised the base structure.
摘要翻译：双极晶体管结构和制造双极晶体管结构的方法包括：（1）至少部分地位于半导体衬底内的集电极结构; （2）与收集器结构接触的基部结构; 和（3）与基底结构接触的发射体结构。发射极结构和基极结构的界面包括氧杂质和选自氟杂质和碳杂质的至少一种杂质，以增强双极晶体管结构内的双极晶体管的性能。杂质可以通过等离子体蚀刻处理或者替代地进行无水氨和氟化氢处理的热处理而引入到界面中，其中基体材料由基底结构组成。

34. 发明授权

US07772028B2 CMOS imager with Cu wiring and method of eliminating high reflectivity interfaces therefrom 失效
标题翻译：具有Cu布线的CMOS成像器和从其中消除高反射率界面的方法
公开(公告)号：US07772028B2
公开(公告)日：2010-08-10
申请号：US11959841
申请日：2007-12-19
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Richard J. Rassel , Anthony K. Stamper
IPC分类号： H01L21/66
CPC分类号： H01L27/14636 , H01L21/76819 , H01L21/76834 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/14629 , H01L27/14645 , H01L27/14683
摘要： A CMOS image sensor and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack to result in a pixel array exhibiting increased light sensitivity. The CMOS image sensor includes structures having a minimum thickness of barrier layer metal that traverses the optical path of each pixel in the sensor array or, that have portions of barrier layer metal selectively removed from the optical paths of each pixel, thereby minimizing reflectance. That is, by implementing various block or single mask methodologies, portions of the barrier layer metal are completely removed at locations of the optical path for each pixel in the array. In a further embodiment, the barrier metal layer may be formed atop the Cu metallization by a self-aligned deposition.
摘要翻译： CMOS图像传感器和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合较薄的层间电介质堆叠以产生呈现增加的光灵敏度的像素阵列。 CMOS图像传感器包括具有穿过传感器阵列中的每个像素的光路的阻挡层金属的最小厚度的结构，或者具有从每个像素的光路中选择性地去除的阻挡层金属的部分，从而使反射率最小化的结构。也就是说，通过实现各种块或单掩模方法，在阵列中的每个像素的光路的位置处完全去除了阻挡层金属的部分。在另一个实施例中，阻挡金属层可以通过自对准沉积形成在Cu金属化之上。

35. 发明授权

US07674705B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US07674705B2
公开(公告)日：2010-03-09
申请号：US12201266
申请日：2008-08-29
申请人： Anthony K. Stamper
发明人： Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/31116 , H01L21/76807 , H01L28/87
摘要： A method of forming a semiconductor device. A first wiring level is formed on a top surface of a substrate. The first wiring level includes alternating layers of a first dielectric material and a second dielectric material. The layers of the first dielectric material includes at least two layers of the first dielectric material. The layers of the second dielectric material includes at least two layers of the second dielectric material. The first dielectric material includes an organic dielectric material. The second dielectric material includes an inorganic dielectric material. The substrate includes one or more dielectric materials. A first layer of the layers of the first dielectric material includes the organic dielectric material being in direct mechanical contact with the substrate. The layers of the first dielectric material and the layers of the second dielectric material are a same number of layers.
摘要翻译：一种形成半导体器件的方法。在基板的顶表面上形成第一布线层。第一布线层包括第一介电材料和第二介电材料的交替层。第一介电材料的层包括至少两层第一介电材料。第二电介质材料的层包括至少两层第二电介质材料。第一电介质材料包括有机介电材料。第二电介质材料包括无机介电材料。衬底包括一种或多种介电材料。第一介电材料层的第一层包括与衬底直接机械接触的有机介电材料。第一介电材料的层和第二介电材料的层是相同数量的层。

36. 发明授权

US07669170B2 Circuit layout methodology using via shape process 失效
标题翻译：使用通孔形状过程的电路布局方法
公开(公告)号：US07669170B2
公开(公告)日：2010-02-23
申请号：US11676185
申请日：2007-02-16
申请人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
发明人： John M. Cohn , Jason Hibbeler , Anthony K. Stamper , Jed H. Rankin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.
摘要翻译：提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。布局迁移工具可用于修改现有布局，以实施新的网格要求。

37. 发明授权

US07659598B2 Semiconductor ground shield 有权
标题翻译：半导体接地屏蔽
公开(公告)号：US07659598B2
公开(公告)日：2010-02-09
申请号：US12371662
申请日：2009-02-16
申请人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
发明人： Mete Erturk , Alvin J. Joseph , Anthony K. Stamper
IPC分类号： H01L29/70
CPC分类号： H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： A ground shield is disclosed that includes a ‘cheesed’ metal positioned within a dielectric layer and a metal region positioned within a first metal level over the cheesed metal. The ground shield can have different forms depending on the metal used, and provisions are made to prevent diffusion of copper (Cu) when that is used as the metal in the cheese metal of the ground shield. The ground shield provides a low resistance, very thick metal at a first metal (M1) level for passive RF elements in conjunction with the standard back-end-of-line (BEOL) integration. The invention also includes a method of forming the ground shield.
摘要翻译：公开了一种接地屏蔽，其包括位于电介质层内的“干酪”金属和位于干酪金属上的第一金属层内的金属区域。接地屏蔽可以根据所使用的金属具有不同的形式，并且当用作接地屏蔽的奶酪金属中的金属时，设置防止铜（Cu）的扩散。接地屏蔽为第一金属（M1）级别提供低电阻，非常厚的金属，用于与标准后端（BEOL）集成结合的无源RF元件。本发明还包括形成接地屏蔽的方法。

38. 发明申请

US20100025857A1 IC CHIP AND DESIGN STRUCTURE WITH THROUGH WAFER VIAS DISHING CORRECTION 有权
标题翻译：通过WAVER VIAS DISHING CORRECTION进行IC芯片和设计结构
公开(公告)号：US20100025857A1
公开(公告)日：2010-02-04
申请号：US12181467
申请日：2008-07-29
申请人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
发明人： Peter J. Lindgren , Edmund J. Sprogis , Anthony K. Stamper
IPC分类号： H01L23/48 , G06F9/45
CPC分类号： H01L21/76898 , H01L21/76838 , H01L21/7684
摘要： An IC chip and design structure having a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV. An IC chip may include a substrate; a through wafer via (TWV) extending through at least one first dielectric layer and into the substrate; a TWV contact contacting the TWV and extending through a second dielectric layer over the TWV; and a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting the TWV contact.
摘要翻译：具有TWV触点的IC芯片和设计结构接触TWV并延伸穿过TWV上的第二介电层。 IC芯片可以包括基板; 穿过至少一个第一电介质层并进入衬底的贯通晶片通孔（TWV）; TWV触点接触TWV并延伸穿过TWV上的第二电介质层; 以及在所述第二电介质层上的第一金属布线层，所述第一金属布线层与所述TWV触点接触。

39. 发明授权

US07655495B2 Damascene copper wiring optical image sensor 有权
标题翻译：大马士革铜线接线光学图像传感器
公开(公告)号：US07655495B2
公开(公告)日：2010-02-02
申请号：US11623977
申请日：2007-01-17
申请人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
发明人： James W. Adkisson , Jeffrey P. Gambino , Mark D. Jaffe , Robert K. Leidy , Anthony K. Stamper
IPC分类号： H01L21/00
CPC分类号： H01L27/14685 , H01L21/76819 , H01L21/76834 , H01L21/76838 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14687
摘要： A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.
摘要翻译： CMOS图像传感器阵列和制造方法，其中传感器包括铜（Cu）金属化水平，允许结合更薄的层间电介质叠层，具有改进的厚度均匀性，以产生呈现增加的光敏度的像素阵列。在传感器阵列中，每个Cu金属化层包括在每个阵列像素之间的位置处形成的Cu金属线结构，并且阻挡材料层形成在穿过像素光路的每个Cu金属线结构上。通过实现单掩模或自对准掩模方法，进行单次蚀刻以完全去除穿过光路的层间电介质层和阻挡层。然后将蚀刻的开口用电介质材料重新填充。在沉积再充填电介质之前，沿蚀刻开口的侧壁形成反射或吸收材料层，以通过将光反射到下面的光电二极管或通过消除光反射来提高像素的灵敏度。

40. 发明申请

US20090316313A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316313A1
公开(公告)日：2009-12-24
申请号：US12144084
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： G06F17/5068 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。

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