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31. 发明申请

US20070114632A1 TRANSISTOR HAVING DIELECTRIC STRESSOR ELEMENTS AT DIFFERENT DEPTHS FROM A SEMICONDUCTOR SURFACE FOR APPLYING SHEAR STRESS 失效
标题翻译：具有用于施加剪切应力的半导体表面的不同深度的介电压力元件的晶体管
公开(公告)号：US20070114632A1
公开(公告)日：2007-05-24
申请号：US11164373
申请日：2005-11-21
申请人： Dureseti Chidambarrao , Brian Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian Greene , Kern Rim
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/6659 , H01L29/7833 , H01L29/7846
摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A buried dielectric stressor element has a horizontally extending upper surface at a first depth below a major surface of a portion of the active semiconductor region, such as an east portion of the active semiconductor region. A surface dielectric stressor element is disposed laterally adjacent to the active semiconductor region at the major surface of the active semiconductor region. The surface dielectric stressor element extends from the major surface to a second depth not substantially greater than the first depth. The stresses applied by the buried and surface dielectric stressor elements cooperate together to apply a shear stress to the channel region of the FET.
摘要翻译：提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。掩埋介质应力元件在有源半导体区域的一部分的主表面下方的第一深度（例如有源半导体区域的东部）处具有水平延伸的上表面。在有源半导体区域的主表面处，表面介电应力元件横向邻近有源半导体区域设置。表面介电应力元件从主表面延伸到不大于第一深度的第二深度。由埋层和表面介电应力元件施加的应力协同工作，对FET的沟道区施加剪切应力。

32. 发明授权

US07932158B2 Formation of improved SOI substrates using bulk semiconductor wafers 有权
标题翻译：使用块状半导体晶片形成改进的SOI衬底
公开(公告)号：US07932158B2
公开(公告)日：2011-04-26
申请号：US12254197
申请日：2008-10-20
申请人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
发明人： William K. Henson , Dureseti Chidambarrao , Kern Rim , Hsingjen Wann , Hung Y. Ng
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L21/76283
摘要： The present invention relates to a semiconductor-on-insulator (SOI) substrate having one or more device regions. Each device region comprises at least a base semiconductor substrate layer and a semiconductor device layer with a buried insulator layer located therebetween, while the semiconductor device layer is supported by one or more vertical insulating pillars. The vertical insulating pillars each preferably has a ledge extending between the base semiconductor substrate layer and the semiconductor device layer. The SOI substrates of the present invention can be readily formed from a precursor substrate structure with a “floating” semiconductor device layer that is spaced apart from the base semiconductor substrate layer by an air gap and is supported by one or more vertical insulating pillars. The air gap is preferably formed by selective removal of a sacrificial layer located between the base semiconductor substrate layer and the semiconductor device layer.
摘要翻译：本发明涉及具有一个或多个器件区域的绝缘体上半导体（SOI）衬底。每个器件区域至少包括基底半导体衬底层和其间设置有掩埋绝缘体层的半导体器件层，而半导体器件层由一个或多个垂直绝缘柱支撑。垂直绝缘柱各自优选地具有在基底半导体衬底层和半导体器件层之间延伸的凸缘。本发明的SOI衬底可以容易地由具有“浮动”半导体器件层的前体衬底结构形成，该半导体器件层通过气隙与基底半导体衬底层间隔开并由一个或多个垂直绝缘柱支撑。气隙优选通过选择性地去除位于基底半导体衬底层和半导体器件层之间的牺牲层来形成。

33. 发明授权

US07838932B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 有权
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07838932B2
公开(公告)日：2010-11-23
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L29/76257
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

34. 发明授权

US07759739B2 Transistor with dielectric stressor elements 失效
标题翻译：具有介电应力元件的晶体管
公开(公告)号：US07759739B2
公开(公告)日：2010-07-20
申请号：US11163683
申请日：2005-10-27
申请人： Dureseti Chidambarrao , Brian J. Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian J. Greene , Kern Rim
IPC分类号： H01L29/94
CPC分类号： H01L21/823481 , H01L21/76232 , H01L21/823412 , H01L29/0653 , H01L29/7846
摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region. The dielectric stressor element shares an edge with the active semiconductor region, the edge extending in a direction away from the upper surface. In particular structures, two or more dielectric stressor elements are provided at locations opposite from each other in the longitudinal and/or transverse directions of the FET.
摘要翻译：提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。具有水平延伸的上表面的介电应激元件在有源半导体区域的一部分的下方延伸。电介质应力元件与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。在特定结构中，在FET的纵向和/或横向方向上彼此相对的位置处提供两个或更多个介电应激元件。

35. 发明授权

US07659581B2 Transistor with dielectric stressor element fully underlying the active semiconductor region 失效
标题翻译：具有完全位于有源半导体区域的介电应力元件的晶体管
公开(公告)号：US07659581B2
公开(公告)日：2010-02-09
申请号：US11164632
申请日：2005-11-30
申请人： Dureseti Chidambarrao , Brian J. Greene , Kern Rim
发明人： Dureseti Chidambarrao , Brian J. Greene , Kern Rim
IPC分类号： H01L31/036
CPC分类号： H01L29/7849 , H01L21/26513 , H01L21/31675 , H01L21/823807 , H01L21/823878 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654
摘要： A compressive stress is applied to a channel region of a PFET by structure including a discrete dielectric stressor element that fully underlies the bottom surface of an active semiconductor region in which the source, drain and channel region of the PFET is disposed. In particular, the dielectric stressor element includes a region of collapsed oxide which fully contacts the bottom surface of the active semiconductor region such that it has an area coextensive with an area of the bottom surface. Bird's beak oxide regions at edges of the dielectric stressor element apply an upward force at edges of the dielectric stressor element to impart a compressive stress to the channel region of the PFET.
摘要翻译：压缩应力通过结构施加到PFET的沟道区域，其包括完全位于其中设置有PFET的源极，漏极和沟道区域的有源半导体区域的底表面的离散介电应激元件。特别地，介电应力元件包括与活性半导体区域的底表面完全接触的塌陷氧化物区域，使得其具有与底表面的区域共同延伸的区域。电介质应力元件边缘处的鸟喙氧化物区域在介质应力元件的边缘施加向上的力，以向PFET的沟道区域施加压应力。

36. 发明授权

US07608489B2 High performance stress-enhance MOSFET and method of manufacture 有权
标题翻译：高性能应力增强型MOSFET及其制造方法
公开(公告)号：US07608489B2
公开(公告)日：2009-10-27
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo A. Donaton , William K. Henson , Kern Rim
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

37. 发明授权

US07473594B2 Raised STI structure and superdamascene technique for NMOSFET performance enhancement with embedded silicon carbon 失效
标题翻译：用嵌入式硅碳纳米管技术，提高了STIFET结构和超级马赛克纳米管的性能提升
公开(公告)号：US07473594B2
公开(公告)日：2009-01-06
申请号：US11459730
申请日：2006-07-25
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

38. 发明申请

US20070254423A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254423A1
公开(公告)日：2007-11-01
申请号：US11380689
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET and varying thickness of the PFET and NFET channel. In one embodiment, the structure enhances the device performance by varying the thickness of the top Silicon layer respective to the NFET or the PFET.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及一种CMOS器件，其具有嵌入在PFET的栅极和源极/漏极区域中以及PFET和NFET沟道的变化厚度的应力诱导材料。在一个实施例中，该结构通过改变相应于NFET或PFET的顶部硅层的厚度来增强器件性能。

39. 发明申请

US20070254422A1 HIGH PERFORMANCE STRESS-ENHANCE MOSFET AND METHOD OF MANUFACTURE 有权
标题翻译：高性能应力增强MOSFET及其制造方法
公开(公告)号：US20070254422A1
公开(公告)日：2007-11-01
申请号：US11380688
申请日：2006-04-28
申请人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
发明人： Dureseti Chidambarrao , Ricardo Donaton , William Henson , Kern Rim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6653 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A semiconductor structure and method of manufacturing and more particularly a CMOS device with a stress inducing material embedded in both gates and also in the source/drain region of the PFET. The PFET region and the NFET region having a different sized gate to vary the device performance of the NFET and the PFET.
摘要翻译：一种半导体结构和制造方法，更具体地说是具有嵌入在PFET的栅极和源极/漏极区域中的应力诱导材料的CMOS器件。 PFET区域和NFET区域具有不同尺寸的栅极，以改变NFET和PFET的器件性能。

40. 发明授权

US07221024B1 Transistor having dielectric stressor elements for applying in-plane shear stress 有权
标题翻译：具有用于施加平面内剪切应力的介电应力元件的晶体管
公开(公告)号：US07221024B1
公开(公告)日：2007-05-22
申请号：US11163686
申请日：2005-10-27
申请人： Dureseti Chidambarrao , Brian J. Green , Kern Rim
发明人： Dureseti Chidambarrao , Brian J. Green , Kern Rim
IPC分类号： H01L27/01
CPC分类号： H01L29/1083 , H01L21/02203 , H01L21/02238 , H01L21/02258 , H01L21/02337 , H01L21/31675 , H01L29/7833 , H01L29/7846
摘要： A chip is provided which includes an active semiconductor region and a field effect transistor (“FET”) having a channel region, a source region and a drain region all disposed within the active semiconductor region. The FET has a longitudinal direction in a direction of a length of the channel region, and a transverse direction in a direction of a width of the channel region. A first dielectric stressor element having a horizontally extending upper surface extends below a portion of the active semiconductor region, such as a northwest portion of the active semiconductor region. A second dielectric stressor element having a horizontally extending upper surface extends below a second portion of the active semiconductor region, such as a southeast portion of the active semiconductor region. Each of the first and second dielectric stressor elements shares an edge with the active semiconductor region, the edges extending in directions away from the upper surface.
摘要翻译：提供一种芯片，其包括有源半导体区域和具有全部设置在有源半导体区域内的沟道区域，源极区域和漏极区域的场效应晶体管（“FET”）。 FET在通道区域的长度方向和沟道区域的宽度方向的横向方向上具有长度方向。具有水平延伸的上表面的第一介电应激元件在有源半导体区域的一部分的下方延伸，例如有源半导体区域的西北部分。具有水平延伸的上表面的第二介电应激元件在有源半导体区域的第二部分的下方延伸，例如有源半导体区域的东南部分。第一和第二介电应力元件中的每一个与有源半导体区域共享边缘，边缘沿远离上表面的方向延伸。

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