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31. 发明申请

US20120025288A1 SOI Trench DRAM Structure With Backside Strap 有权
标题翻译： SOI沟槽DRAM结构带背面带
公开(公告)号：US20120025288A1
公开(公告)日：2012-02-02
申请号：US12847208
申请日：2010-07-30
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/8242 , H01L27/108 , H01L21/02
CPC分类号： H01L27/1203 , H01L27/10829 , H01L27/10867
摘要： In one exemplary embodiment, a semiconductor structure including: a silicon-on-insulator substrate having of a top silicon layer overlying an insulation layer, where the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, where at least a first portion of the backside strap underlies the doped portion of the top silicon layer, where the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, where the second epitaxially-deposited material further at least partially overlies the first portion of the backside strap.
摘要翻译：在一个示例性实施例中，一种半导体结构，包括：绝缘体上硅衬底，其具有覆盖绝缘层的顶部硅层，其中所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，其中背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，其中背面带在顶部硅层的第一端处耦合到顶部硅层的掺杂部分背面带和在背面带的第二端处的电容器; 以及第二外延沉积材料，其至少部分地覆盖在顶部硅层的掺杂部分上，其中第二外延沉积材料进一步至少部分地覆盖在背面带的第一部分上。

32. 发明申请

US20110291202A1 DEVICE AND METHOD OF REDUCING JUNCTION LEAKAGE 有权
标题翻译：减少接头泄漏的装置和方法
公开(公告)号：US20110291202A1
公开(公告)日：2011-12-01
申请号：US12789839
申请日：2010-05-28
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66628 , H01L21/26513 , H01L29/0847 , H01L29/41783 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834
摘要： A device and method for reducing junction leakage in a semiconductor junction includes forming a faceted raised structure in a source/drain region of the device. Dopants are diffused from the faceted raised structure into a substrate below the faceted raised structure to form source/drain regions. A sprinkle implantation is applied on the faceted raised structure to produce a multi-depth dopant profile in the substrate for the source/drain regions.
摘要翻译：用于减少半导体结中的结漏电的器件和方法包括在器件的源极/漏极区域中形成刻面的凸起结构。掺杂剂从小面凸起结构扩散到小平面凸起结构下面的基底中以形成源极/漏极区域。在刻面凸起结构上施加喷洒注入，以在源/漏区的衬底中产生多深度掺杂物分布。

33. 发明申请

US20110291100A1 DEVICE AND METHOD FOR FABRICATING THIN SEMICONDUCTOR CHANNEL AND BURIED STRAIN MEMORIZATION LAYER 有权
标题翻译：用于制造半导体通道和BURIED应力记忆层的装置和方法
公开(公告)号：US20110291100A1
公开(公告)日：2011-12-01
申请号：US12789792
申请日：2010-05-28
申请人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： KANGGUO CHENG , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/10 , H01L21/20
CPC分类号： H01L29/7847 , H01L21/02532 , H01L21/02664 , H01L21/26506 , H01L29/7841 , H01L29/785
摘要： A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
摘要翻译：用于在半导体层中诱发应力的装置和方法包括提供具有形成在第一半导体层和第二半导体层之间的介电层的衬底，并且处理第二半导体层以形成非晶化材料。应力层沉积在第一半导体层上。将晶片退火以通过使非晶化材料重结晶来在第二半导体层中记忆应力。

34. 发明申请

US20110175166A1 STRAINED CMOS DEVICE, CIRCUIT AND METHOD OF FABRICATION 有权
标题翻译：应变CMOS器件，电路和制造方法
公开(公告)号：US20110175166A1
公开(公告)日：2011-07-21
申请号：US12689339
申请日：2010-01-19
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7849
摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.
摘要翻译：半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

35. 发明申请

US20110068396A1 METHOD AND STRUCTURE FOR FORMING HIGH-PERFOMANCE FETs WITH EMBEDDED STRESSORS 有权
标题翻译：用嵌入式压力器形成高性能FET的方法和结构
公开(公告)号：US20110068396A1
公开(公告)日：2011-03-24
申请号：US12566004
申请日：2009-09-24
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/2257 , H01L21/26586 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
摘要翻译：提供了高性能半导体结构和制造这种结构的方法。半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

36. 发明授权

US08860138B2 Strained thin body CMOS device having vertically raised source/drain stressors with single spacer 有权
公开(公告)号：US08860138B2
公开(公告)日：2014-10-14
申请号：US13531053
申请日：2012-06-22
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L29/66 , H01L29/78 , H01L29/786 , H01L21/84 , H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

37. 发明授权

US08598663B2 Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions 失效
标题翻译：具有NFET和PFET的半导体结构形成在具有延伸延伸的SOI衬底中
公开(公告)号：US08598663B2
公开(公告)日：2013-12-03
申请号：US13108290
申请日：2011-05-16
申请人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/02 , H01L29/786 , H01L21/70
CPC分类号： H01L27/1203 , H01L21/823864 , H01L21/823892
摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.
摘要翻译：一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。每个NFET和PFET下面也可以有一个阱。存在将非零电偏压施加到SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

38. 发明授权

US08536032B2 Formation of embedded stressor through ion implantation 有权
标题翻译：通过离子注入形成嵌入式应激源
公开(公告)号：US08536032B2
公开(公告)日：2013-09-17
申请号：US13155878
申请日：2011-06-08
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L21/265
CPC分类号： H01L29/66772 , H01L29/7848 , H01L29/7849 , H01L29/78654
摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.
摘要翻译：极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。掩埋氧化物层例如具有小于50nm的厚度。硅层在掩埋氧化物层之上。硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。

39. 发明授权

US08513765B2 Formation method and structure for a well-controlled metallic source/drain semiconductor device 有权
标题翻译：良好控制的金属源/漏极半导体器件的形成方法和结构
公开(公告)号：US08513765B2
公开(公告)日：2013-08-20
申请号：US12838844
申请日：2010-07-19
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/02
CPC分类号： H01L29/7839 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/66795
摘要： A device and method for forming a semiconductor device include growing a raised semiconductor region on a channel layer adjacent to a gate structure. A space is formed between the raised semiconductor region and the gate structure. A metal layer is deposited on at least the raised semiconductor region. The raised semiconductor region is silicided to form a silicide into the channel layer which extends deeper into the channel layer at a position corresponding to the space.
摘要翻译：用于形成半导体器件的器件和方法包括在与栅极结构相邻的沟道层上生长凸起的半导体区域。在凸起的半导体区域和栅极结构之间形成空间。在至少凸起的半导体区域上沉积金属层。凸起的半导体区域被硅化以在通道层中形成硅化物，该沟道层在对应于空间的位置处更深地延伸到沟道层中。

40. 发明授权

US08492839B2 Same-chip multicharacteristic semiconductor structures 有权
标题翻译：同芯片多特征半导体结构
公开(公告)号：US08492839B2
公开(公告)日：2013-07-23
申请号：US12861976
申请日：2010-08-24
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1211 , H01L27/1203
摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.
摘要翻译：在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

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