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31. 发明申请

US20090085027A1 THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD 有权
标题翻译：通过三维尺寸应变量子阱和三维应变表面通道
公开(公告)号：US20090085027A1
公开(公告)日：2009-04-02
申请号：US11864963
申请日：2007-09-29
申请人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
发明人： Been-Yih Jin , Robert S. Chau , Brian S. Doyle , Jack T. Kavalieros
IPC分类号： H01L29/12 , H01L21/205
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02664 , H01L29/0673 , H01L29/1054 , H01L29/66818 , H01L29/7851
摘要： The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开描述了通过Ge约束法实现3D（三维）应变高迁移量子阱结构和3D应变表面通道结构的方法和装置。一个示例性设备可以包括在Si衬底上的第一梯度SiGe鳍。第一级的SiGe鳍可以具有大于约60％的最大Ge浓度。 Ge量子阱可以在第一等级的SiGe鳍上，SiGe量子阱上阻挡层可以在Ge量子阱上。示例性设备还可以包括在Si衬底上的第二渐变SiGe鳍。第二级的SiGe鳍可以具有小于约40％的最大Ge浓度。 Si活性沟道层可以在第二级别的SiGe鳍上。可以使用诸如III-V族半导体的其它高迁移率材料作为活性通道材料。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

32. 发明授权

US07821061B2 Silicon germanium and germanium multigate and nanowire structures for logic and multilevel memory applications 有权
标题翻译：用于逻辑和多级存储器应用的硅锗和锗多重和纳米线结构
公开(公告)号：US07821061B2
公开(公告)日：2010-10-26
申请号：US11729565
申请日：2007-03-29
申请人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
发明人： Been-Yih Jin , Brian S. Doyle , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/00
CPC分类号： H01L21/02381 , B82Y10/00 , H01L21/02164 , H01L21/02236 , H01L21/0245 , H01L21/02507 , H01L21/02532 , H01L21/02603 , H01L21/30604 , H01L21/31658 , H01L21/76283 , H01L21/823807 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/1054 , H01L29/165 , H01L29/42324 , H01L29/42392 , H01L29/66439 , H01L29/66795 , H01L29/66818 , H01L29/775 , H01L29/785 , H01L29/78696
摘要： A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.
摘要翻译：一种提供晶体管或存储单元结构的方法。该方法包括：在衬底上提供包括下Si衬底和绝缘层的衬底; 提供在所述绝缘层上方延伸的第一突起，所述第一突起包括Si材料和Si1-xGex材料; 以及将所述第一突起暴露于优先氧化以产生包括包含Ge / Si1-yGey的中心区域和包含SiO 2并包围所述中心区域的覆盖区域的第二突起。

33. 发明授权

US07485536B2 Abrupt junction formation by atomic layer epitaxy of in situ delta doped dopant diffusion barriers 有权
标题翻译：通过原子层外延原位δ掺杂掺杂剂扩散阻挡层的突变结形成
公开(公告)号：US07485536B2
公开(公告)日：2009-02-03
申请号：US11326178
申请日：2005-12-30
申请人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
发明人： Been-Yih Jin , Brian S. Doyle , Robert S. Chau , Jack T. Kavalieros
IPC分类号： H01L21/335
CPC分类号： H01L29/0847 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7851
摘要： A method including forming a channel region between source and drain regions in a substrate, the channel region including a first dopant profile; and forming a barrier layer between the channel region and a well of the substrate, the barrier layer including a second dopant profile different from the first dopant profile. An apparatus including a gate electrode on a substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region, the barrier layer including a dopant profile different than a dopant profile of the channel region and different than a dopant profile of the well. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices formed in a substrate, each of the plurality of transistor devices including a gate electrode on the substrate; source and drain regions formed in the substrate and separated by a channel region; and a barrier layer between a well of the substrate and the channel region.
摘要翻译：一种方法，包括在衬底中的源区和漏区之间形成沟道区，所述沟道区包括第一掺杂物分布; 以及在所述沟道区和所述衬底的阱之间形成阻挡层，所述阻挡层包括不同于所述第一掺杂剂分布的第二掺杂剂分布。一种在基板上包括栅电极的装置; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及在衬底的阱和沟道区之间的阻挡层，阻挡层包括不同于沟道区的掺杂物分布并且不同于阱的掺杂剂分布的掺杂剂分布。一种包括包括微处理器的计算设备的系统，所述微处理器包括形成在衬底中的多个晶体管器件，所述多个晶体管器件中的每一个在所述衬底上包括栅电极; 源极和漏极区域形成在衬底中并被沟道区域分离; 以及衬底的阱和沟道区之间的阻挡层。

34. 发明申请

US20060292776A1 Strained field effect transistors 审中-公开
标题翻译：应变场效应晶体管
公开(公告)号：US20060292776A1
公开(公告)日：2006-12-28
申请号：US11167647
申请日：2005-06-27
申请人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
发明人： Been-Yih Jin , Robert Chau , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Mark Doczy , Matthew Metz , Markus Kuhn , Marko Radosavlievic , M. Shaheed , Patrick Keys
IPC分类号： H01L21/8234 , H01L21/20 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L27/0922 , H01L29/1054 , H01L29/165 , H01L29/7848
摘要： An NMOS transistor may be formed with a biaxially strained silicon upper layer having a thickness of greater than 500 Angstroms. The resulting NMOS transistor may have good performance and may exhibit reduced self-heating. A PMOS transistor may be formed with both a biaxially and uniaxially strained silicon germanium layer. A source substrate bias applied to both NMOS and PMOS transistors can enhance their performance.
摘要翻译： NMOS晶体管可以形成为具有大于500埃的厚度的双轴应变硅上层。所得的NMOS晶体管可以具有良好的性能并且可以表现出减少的自热。 PMOS晶体管可以形成为双轴和单轴应变的硅锗层。施加到NMOS和PMOS晶体管的源极衬底偏置可以提高其性能。

35. 发明申请

US20160049513A1 TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR FINS 有权
标题翻译：用于非均匀应变半导体FINS的二维冷凝
公开(公告)号：US20160049513A1
公开(公告)日：2016-02-18
申请号：US14882440
申请日：2015-10-13
申请人： Jack T. Kavalieros , Nancy Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
发明人： Jack T. Kavalieros , Nancy Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
IPC分类号： H01L29/78 , H01L29/10 , H01L29/165
CPC分类号： H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/66818 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
摘要翻译：公开了用于实现半导体翅片的多面冷凝的技术。这些技术可以用于例如制造基于鳍的晶体管。在一个示例的情况下，在体基板上设置应变层。应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

36. 发明申请

US20140103396A1 STRAIN-INDUCING SEMICONDUCTOR REGIONS 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US20140103396A1
公开(公告)日：2014-04-17
申请号：US14133457
申请日：2013-12-18
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/10 , H01L29/78
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

37. 发明授权

US08120065B2 Tensile strained NMOS transistor using group III-N source/drain regions 有权
标题翻译：使用III-N族源/漏区的拉伸应变NMOS晶体管
公开(公告)号：US08120065B2
公开(公告)日：2012-02-21
申请号：US12541763
申请日：2009-08-14
申请人： Suman Datta , Justin K. Brask , Been-Yih Jin , Jack T. Kavalieros , Mantu K. Hudait
发明人： Suman Datta , Justin K. Brask , Been-Yih Jin , Jack T. Kavalieros , Mantu K. Hudait
IPC分类号： H01L21/02
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/517 , H01L29/66628 , H01L29/7848 , Y10S438/933 , Y10S438/938
摘要： Enhancement mode transistors are described where a Group III-N compound is used in the source and drain regions to place tensile strain on the channel. The source and drain regions may be raised or embedded, and fabricated in conjunction with recessed or raised compression regions for p channel transistors.
摘要翻译：描述了增强模式晶体管，其中在源极和漏极区域中使用III-N族化合物以在通道上施加拉伸应变。源极和漏极区域可以被凸起或嵌入，并且与用于p沟道晶体管的凹陷或凸起的压缩区域一起制造。

38. 发明申请

US20090170267A1 Tri-gate patterning using dual layer gate stack 有权
标题翻译：使用双层栅极堆叠的三栅极图案化
公开(公告)号：US20090170267A1
公开(公告)日：2009-07-02
申请号：US12006047
申请日：2007-12-28
申请人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
发明人： Uday Shah , Brian S. Doyle , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L21/336
CPC分类号： H01L21/823821 , H01L29/66795 , H01L29/785
摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A ploysilicon layer is formed over the silicon germanium layer and is polished. The ploysilicon layer over the first work function metal layer is thicker than the ploysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the ploysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.
摘要翻译：通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。在衬底上形成高介电常数层。在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。在第一和第二功函数金属层上形成硅锗层。在硅锗层上方形成硅层，并进行抛光。第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。硬掩模被图案化并用于蚀刻合金层和硅锗层以产生栅极堆叠。硅锗层的蚀刻速率比第一功函数金属层更快。

39. 发明授权

US08530884B2 Strain inducing semiconductor regions 有权
标题翻译：应变诱导半导体区域
公开(公告)号：US08530884B2
公开(公告)日：2013-09-10
申请号：US13160886
申请日：2011-06-15
申请人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
发明人： Suman Datta , Jack T. Kavalieros , Been-Yih Jin
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/1033 , H01L29/0673 , H01L29/201 , H01L29/205 , H01L29/41725 , H01L29/66431 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66787 , H01L29/775 , H01L29/78 , H01L29/785
摘要： A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.
摘要翻译：描述形成应变诱导半导体区域的方法。在一个实施方案中，形成横向邻近晶体衬底的应变诱导半导体区域导致赋予晶体衬底的单轴应变，从而提供应变的晶体衬底。在另一个实施方案中，具有一种或多种电荷 - 中性晶格形成原子的晶格的半导体区域向晶体衬底赋予应变，其中半导体区域的晶格常数与晶体衬底的晶格常数不同，以及其中所述半导体区域的电荷 - 中性晶格形成原子的所有种类都包含在所述晶体衬底中。

40. 发明授权

US08211772B2 Two-dimensional condensation for uniaxially strained semiconductor fins 有权
标题翻译：用于单轴应变半导体翅片的二维冷凝
公开(公告)号：US08211772B2
公开(公告)日：2012-07-03
申请号：US12646427
申请日：2009-12-23
申请人： Jack T. Kavalieros , Nancy M. Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
发明人： Jack T. Kavalieros , Nancy M. Zelick , Been-Yih Jin , Markus Kuhn , Stephen M. Cea
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/66795 , H01L29/66818 , H01L29/7842 , H01L29/7849 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要： Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
摘要翻译：公开了用于实现半导体翅片的多面冷凝的技术。这些技术可以用于例如制造基于鳍的晶体管。在一个示例的情况下，在体基板上设置应变层。应变层与取决于应变层的部件的临界厚度相关联，并且应变层具有低于或等于临界厚度的厚度。在基板和应变层中形成翅片，使得翅片包括基板部分和应变层部分。将翅片氧化以冷凝翅片的应变层部分，使得应变层中的组分的浓度从预凝结浓度变为较高的缩合后浓度，从而超过临界厚度。

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