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31. 发明申请

US20080261361A1 Shallow trench isolation for SOI structures combining sidewall spacer and bottom liner 有权
标题翻译：浅沟槽隔离用于结合侧墙和底衬的SOI结构
公开(公告)号：US20080261361A1
公开(公告)日：2008-10-23
申请号：US11788184
申请日：2007-04-18
申请人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
发明人： Konstantin V. Loiko , Toni D. Van Gompel , Rode R. Mora , Michael D. Turner , Brian A. Winstead , Mark D. Hall
IPC分类号： H01L21/8238 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/823864 , H01L21/823878 , H01L21/84 , H01L29/0649 , H01L29/16 , H01L29/161 , H01L29/66477 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.
摘要翻译：提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和布置在所述衬底和所述半导体层之间的介电层（209）的层堆叠，（b）产生沟槽（210）其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

32. 发明授权

US06249035B1 LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect 失效
标题翻译： LOCOS掩模用于抑制窄空间场氧化物稀化和氧化物穿透效应
公开(公告)号：US06249035B1
公开(公告)日：2001-06-19
申请号：US09480268
申请日：2000-01-11
申请人： Igor V. Peidous , Quek Kiok Boone Elgin , Konstantin V. Loiko , Tan Poh Suan , Vijai Kumar N. Chhagan
发明人： Igor V. Peidous , Quek Kiok Boone Elgin , Konstantin V. Loiko , Tan Poh Suan , Vijai Kumar N. Chhagan
IPC分类号： H01L2900
CPC分类号： H01L21/7621
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of oxide punch though and the narrow oxide thinning effect.
摘要翻译：一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。掩模在其下边缘处使用薄的锥形氮化硅脚，以在氧化的早期阶段允许氧化物的标称膨胀，从而允许原位应力释放以及氧化物轮廓的平滑化。脚的锥度提供了掩模刚度逐渐增加，因为在掩模边缘下进行氧化，允许在早期快速生长期期间具有最大的灵活性，随后在生长速率减慢的后期阶段增加刚度，由此抑制鸟的渗透喙。负责位错生成的剪切应力减少了五十倍。这种应力降低伴随着表面形貌的改善以及氧化物冲击的抑制以及窄的氧化物稀化效应。

33. 发明授权

US5894059A Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect 失效
公开(公告)号：US5894059A
公开(公告)日：1999-04-13
申请号：US866776
申请日：1997-05-30
申请人： Igor V. Peidous , Konstantin V. Loiko , Elgin Quek , David Yeo Yong Hock
发明人： Igor V. Peidous , Konstantin V. Loiko , Elgin Quek , David Yeo Yong Hock
IPC分类号： H01L21/033 , H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/32 , H01L21/0332 , H01L21/76202 , Y10S438/95
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.

34. 发明申请

US20090042351A1 METHOD FOR MAKING A TRANSISTOR WITH A STRESSOR 有权
标题翻译：制造带有压力器的晶体管的方法
公开(公告)号：US20090042351A1
公开(公告)日：2009-02-12
申请号：US11835547
申请日：2007-08-08
申请人： Xiangzheng Bo , Venkat R. Kolagunta , Konstantin V. Loiko
发明人： Xiangzheng Bo , Venkat R. Kolagunta , Konstantin V. Loiko
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/4958 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
摘要翻译：在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。该方法还包括在半导体材料层中形成源极/漏极区域。该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。

35. 发明授权

US06380610B1 Dislocation free local oxidation of silicon with suppression of narrow space field oxide thinning effect 失效
标题翻译：无位错局部氧化硅，抑制窄空间场氧化物稀化效应
公开(公告)号：US06380610B1
公开(公告)日：2002-04-30
申请号：US09257838
申请日：1999-02-25
申请人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
发明人： Igor V. Peidous , Elgin Quek , Konstantin V. Loiko , David Yeo Yong Hock
IPC分类号： H01L2358
CPC分类号： H01L21/32 , H01L21/0332 , H01L21/76202 , Y10S438/95
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. A cantilevered portion of a second, thicker silicon nitride layer suppresses the upward movement of the flexible foot during the later stages of the oxidation when the growth rate has slowed, thereby inhibiting the growth of the birds beak. Shear stresses responsible for dislocation generation are reduced as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of the narrow oxide thinning effect.
摘要翻译：一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。掩模在其下边缘处使用薄的氮化硅脚，以允许在氧化的早期阶段氧化物的标称膨胀，从而允许原位应力消除以及氧化物轮廓的平滑化。第二较厚的氮化硅层的悬臂部分在生长速度减慢时在氧化的后期阶段抑制柔性脚的向上移动，由此抑制鸟喙的生长。负责位错生成的剪切应力减少了五十倍。这种应力降低伴随着表面形貌的改善以及窄的氧化物稀化效应的抑制。

36. 发明授权

US6071793A Locos mask for suppression of narrow space field oxide thinning and oxide punch through effect 失效
标题翻译：用于抑制窄空间场氧化物变薄和氧化物穿孔效果的Locos掩模
公开(公告)号：US6071793A
公开(公告)日：2000-06-06
申请号：US17141
申请日：1998-02-02
申请人： Igor V. Peidous , Quek Kiok Boone Elgin , Konstantin V. Loiko , Tan Poh Suan , Vijai Kumar N. Chhagan
发明人： Igor V. Peidous , Quek Kiok Boone Elgin , Konstantin V. Loiko , Tan Poh Suan , Vijai Kumar N. Chhagan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/7621
摘要： A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold. This stress reduction is accompanied by an improvement in surface topography as well as suppression of oxide punchthough and the narrow oxide thinning effect.
摘要翻译：一种用于改善鸟喙控制的氧化面罩的新颖设计，更具体地用于在鸟喙附近调整和平滑场氧化物隔离轮廓。掩模设计对于半微米集成电路技术中的窄场隔离间隔特别有利。掩模在其下边缘处使用薄的锥形氮化硅脚，以在氧化的早期阶段允许氧化物的标称膨胀，从而允许原位应力释放以及氧化物轮廓的平滑化。脚的锥度提供了掩模刚度逐渐增加，因为在掩模边缘下进行氧化，允许在早期快速生长期期间具有最大的灵活性，随后在生长速率减慢的后期阶段增加刚度，由此抑制鸟的渗透喙。负责位错生成的剪切应力减少了五十倍。这种应力降低伴随着表面形貌的改善以及氧化物冲击的抑制和窄的氧化物稀化效应。

37. 发明授权

US07799650B2 Method for making a transistor with a stressor 有权
标题翻译：制造具有应激源的晶体管的方法
公开(公告)号：US07799650B2
公开(公告)日：2010-09-21
申请号：US11835547
申请日：2007-08-08
申请人： Xiangzheng Bo , Venkat R. Kolagunta , Konstantin V. Loiko
发明人： Xiangzheng Bo , Venkat R. Kolagunta , Konstantin V. Loiko
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L29/4958 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.
摘要翻译：在半导体材料层上形成半导体器件的方法包括在半导体材料层上形成栅极结构。该方法还包括形成邻近栅极结构的第一氮化物间隔区，并在半导体材料层中形成源极/漏极延伸部分。该方法还包括形成覆盖栅极结构和源极/漏极延伸部的氧化物衬垫。该方法还包括在氧化物衬垫附近形成第二氮化物间隔物。该方法还包括在半导体材料层中形成源/漏区。该方法还包括使用对氧化物衬垫有选择性的蚀刻工艺，去除第二氮化物间隔物。该方法还包括使用对第一氮化物间隔物具有选择性的蚀刻工艺，至少部分地去除氧化物衬垫。该方法还包括形成覆盖源极/漏极区域和栅极结构的硅化物区域。

38. 发明授权

US07521314B2 Method for selective removal of a layer 有权
标题翻译：选择性去除层的方法
公开(公告)号：US07521314B2
公开(公告)日：2009-04-21
申请号：US11738192
申请日：2007-04-20
申请人： Dharmesh Jawarani , Konstantin V. Loiko , Andrew G. Nagy
发明人： Dharmesh Jawarani , Konstantin V. Loiko , Andrew G. Nagy
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/4763
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.
摘要翻译：一种用于形成半导体器件的方法包括在包括控制电极的半导体材料上形成衬垫。该方法还包括形成与控制电极相邻的第一间隔物，其中第一间隔物具有第一宽度。该方法还包括植入电流电极掺杂剂。该方法还包括移除第一间隔物。该方法还包括形成邻近控制电极的第二间隔物，其中第二间隔物具有第二宽度，并且其中第二宽度小于第一宽度。该方法还包括使用第二间隔件作为保护罩以选择性地移除衬垫。该方法还包括形成覆盖控制电极和电流电极区域的应力源层。

39. 发明申请

US20080261385A1 METHOD FOR SELECTIVE REMOVAL OF A LAYER 有权
标题翻译：选择性去除层的方法
公开(公告)号：US20080261385A1
公开(公告)日：2008-10-23
申请号：US11738192
申请日：2007-04-20
申请人： Dharmesh Jawarani , Konstantin V. Loiko , Andrew G. Nagy
发明人： Dharmesh Jawarani , Konstantin V. Loiko , Andrew G. Nagy
IPC分类号： H01L21/311 , H01L21/266
CPC分类号： H01L29/7843 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method for forming a semiconductor device includes forming a liner over a semiconductor material including a control electrode. The method further includes forming a first spacer adjacent to the control electrode, wherein the first spacer has a first width. The method further includes implanting current electrode dopants. The method further includes removing the first spacer. The method further includes forming a second spacer adjacent the control electrode, wherein the second spacer has a second width and wherein the second width is less than the first width. The method further includes using the second spacer as a protective mask to selectively remove the liner. The method further includes forming a stressor layer overlying the control electrode and current electrode regions.
摘要翻译：一种用于形成半导体器件的方法包括在包括控制电极的半导体材料上形成衬垫。该方法还包括形成与控制电极相邻的第一间隔物，其中第一间隔物具有第一宽度。该方法还包括植入电流电极掺杂剂。该方法还包括移除第一间隔物。该方法还包括形成邻近控制电极的第二间隔物，其中第二间隔物具有第二宽度，并且其中第二宽度小于第一宽度。该方法还包括使用第二间隔件作为保护罩以选择性地移除衬垫。该方法还包括形成覆盖控制电极和电流电极区域的应力源层。

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