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31. 发明授权

US07402850B2 Back-side trapped non-volatile memory device 有权
标题翻译：背面捕获的非易失性存储器件
公开(公告)号：US07402850B2
公开(公告)日：2008-07-22
申请号：US11157361
申请日：2005-06-21
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/74
CPC分类号： H01L29/792 , B82Y10/00 , G11C16/0416 , G11C16/0483 , H01L21/28273 , H01L21/84 , H01L27/11521 , H01L29/4232 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.
摘要翻译：描述了非易失性存储器件和阵列，其利用具有带不对称隧道势垒的带隙工程化栅极堆叠的背侧捕获的浮动节点存储器单元。本发明的实施例允许直接隧道编程和用电子和空穴的有效擦除，同时保持高电荷阻挡屏障和深载流子捕获位点，以实现良好的电荷保持，并减少损坏通道/绝缘体界面的可能性。直接隧道程序和有效的擦除能力降低了高能量载体对栅极堆叠和晶格的损害，减少了写入疲劳和泄漏问题，并增强了器件寿命。呈现本发明的存储器件实施例，其被布置在NOR或NAND存储器架构阵列中。本发明的存储单元实施例还允许单个存储单元中的多个位存储，并允许以降低的电压进行编程和擦除。

32. 发明授权

US07358131B2 Methods of forming SRAM constructions 失效
标题翻译：形成SRAM结构的方法
公开(公告)号：US07358131B2
公开(公告)日：2008-04-15
申请号：US11350201
申请日：2006-02-08
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L21/8238
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/12 , H01L27/1203 , H01L2924/0002 , Y10S257/903 , Y10S257/904 , H01L2924/00
摘要： The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.
摘要翻译：本发明包括SRAM构造，其包括至少一个晶体管器件，其具有延伸到包含Si / Ge的晶体层的有源区域。晶体层内的主要区域的大部分在晶体层的单晶内，特别地，结晶层内的整个有源区域在结晶层的单晶内。 SRAM结构可以形成在半导体绝缘体组件上，并且这种组件可以由各种基板支撑，包括例如玻璃，半导体衬底，金属，绝缘材料和塑料。本发明还包括包括SRAM结构的电子系统。

33. 发明申请

US20080057690A1 Tantalum silicon oxynitride high-k dielectrics and metal gates 有权
标题翻译：钽硅氮氧化物高k电介质和金属栅极
公开(公告)号：US20080057690A1
公开(公告)日：2008-03-06
申请号：US11514601
申请日：2006-08-31
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/3205
CPC分类号： H01L21/0215 , C23C16/308 , H01L21/0223 , H01L21/02255 , H01L21/02332 , H01L21/0234 , H01L21/28079 , H01L21/28273 , H01L21/3141 , H01L21/3145 , H01L21/31637 , H01L28/40 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545
摘要： Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的基板上的钽氮氧化硅膜。钽氮氧化硅膜可以被构造为一个或多个单层。可以使用原子层沉积形成钽氮氧化硅膜。金属电极可以设置在包含钽氮氧化硅膜的电介质上。

34. 发明申请

US20080057659A1 Hafnium aluminium oxynitride high-K dielectric and metal gates 审中-公开
标题翻译：铪铝氮氧化物高K电介质和金属门
公开(公告)号：US20080057659A1
公开(公告)日：2008-03-06
申请号：US11514558
申请日：2006-08-31
申请人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
发明人： Leonard Forbes , Kie Y. Ahn , Arup Bhattacharyya
IPC分类号： H01L21/20
CPC分类号： H01L21/02194 , C23C16/0227 , C23C16/308 , C23C16/34 , C23C16/40 , C23C16/45531 , C23C16/56 , H01L21/022 , H01L21/0223 , H01L21/02255 , H01L21/0228 , H01L21/02332 , H01L21/0234 , H01L21/28194 , H01L21/28202 , H01L21/28229 , H01L21/3141 , H01L21/3143 , H01L21/31604 , H01L21/31645 , H01L21/318 , H01L29/4908 , H01L29/517 , H01L29/518 , H01L29/7833
摘要： Electronic apparatus and methods of forming the electronic apparatus include a hafnium aluminum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium aluminum oxynitride film may be structured as one or more monolayers. The hafnium aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium aluminum oxynitride film.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的基板上的铪铝氮氧化物膜。铪铝氮氧化物膜可以被构造为一个或多个单层。可以使用原子层沉积形成铪铝氮氧化物膜。金属电极可以设置在含有铪铝氮氧化物膜的电介质上。

35. 发明申请

US20080009117A1 Band-engineered multi-gated non-volatile memory device with enhanced attributes 有权
标题翻译：带改进的多门控非易失性存储器件具有增强的属性
公开(公告)号：US20080009117A1
公开(公告)日：2008-01-10
申请号：US11900595
申请日：2007-09-12
申请人： Arup Bhattacharyya , Kirk Prall , Luan Tran
发明人： Arup Bhattacharyya , Kirk Prall , Luan Tran
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0433 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/115 , H01L29/513
摘要： Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.
摘要翻译：描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。还提供了正电压擦除处理通孔隧穿。

36. 发明申请

US20070238320A1 Devices and methods to improve carrier mobility 有权
标题翻译：改善载波移动性的装置和方法
公开(公告)号：US20070238320A1
公开(公告)日：2007-10-11
申请号：US11398809
申请日：2006-04-06
申请人： Arup Bhattacharyya , Leonard Forbes
发明人： Arup Bhattacharyya , Leonard Forbes
IPC分类号： H01L21/31
CPC分类号： H01L21/0214 , H01L21/02271 , H01L21/0228 , H01L21/28282 , H01L21/31111 , H01L21/3144 , H01L21/3145 , H01L21/823807 , H01L21/823864 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L29/1054 , H01L29/6659 , H01L29/66833 , H01L29/7833 , H01L29/7834 , H01L29/7843 , H01L29/7848
摘要： Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.
摘要翻译：形成电子设备的电子设备和方法包括用于各种电子系统的半导体器件上的氮氧化硅层。氧氮化硅层可以被构造为控制半导体器件的硅沟道中的应变以改善硅沟道中的载流子迁移率，其中硅沟道被配置为在半导体器件的合适的工作条件下传导电流。

37. 发明授权

US07279740B2 Band-engineered multi-gated non-volatile memory device with enhanced attributes 有权
标题翻译：带改进的多门控非易失性存储器件具有增强的属性
公开(公告)号：US07279740B2
公开(公告)日：2007-10-09
申请号：US11127618
申请日：2005-05-12
申请人： Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
发明人： Arup Bhattacharyya , Kirk D. Prall , Luan C. Tran
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C16/0433 , G11C16/0466 , G11C16/0475 , G11C16/0483 , H01L27/115 , H01L29/513
摘要： Non-volatile memory devices and arrays are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in floating gate memory cells in NOR or NAND memory architectures that allow for direct tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory cells of the present invention also allow multiple bit storage in a single memory cell, and allow for programming and erase with reduced voltages. A positive voltage erase process via hole tunneling is also provided.
摘要翻译：描述了非易失性存储器件和阵列，其有助于在NOR或NAND存储器架构中的浮动栅极存储器单元中使用具有非对称隧道势垒的带隙工程化栅极堆叠，这允许直接隧道编程和用电子和空穴擦除，同时保持高电荷阻挡屏障和深载体捕获位点，具有良好的电荷保留性。直接隧道编程和擦除功能可以减少高能量载体对栅极堆叠和晶格的损害，减少写入疲劳和泄漏问题，并增强器件寿命。本发明的存储器单元还允许在单个存储器单元中进行多位存储，并允许以降低的电压进行编程和擦除。还提供了正电压擦除处理通孔隧穿。

38. 发明申请

US20070132010A1 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier 有权
标题翻译：具有谐振隧道势垒的增强型多位非易失性存储器件
公开(公告)号：US20070132010A1
公开(公告)日：2007-06-14
申请号：US11298884
申请日：2005-12-09
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L21/28273 , G11C11/56 , G11C16/0466 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/792
摘要： A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or LaAlO3. A charge trapping layer is formed over the tunnel barrier. A high-k charge blocking layer is formed over the charge trapping layer. A control gate is formed over the charge blocking layer. Another embodiment forms a floating gate over the tunnel barrier that is comprised of two oxide layers with an amorphous layer of silicon and/or germanium between the oxide layers.
摘要翻译：非易失性存储单元使用谐振隧道势垒，其在HfSiON或LaAlO 3 3的两层之间具有非晶硅和/或非晶锗层。在隧道势垒上形成电荷俘获层。在电荷捕获层上形成高k电荷阻挡层。控制栅极形成在电荷阻挡层上。另一个实施例在隧道势垒上形成浮动栅极，该栅极由在氧化物层之间具有硅和/或锗的非晶层的两个氧化物层组成。

39. 发明授权

US07221026B2 Computer systems containing resistors which include doped silicon/germanium 有权
标题翻译：包含掺杂硅/锗的电阻的计算机系统
公开(公告)号：US07221026B2
公开(公告)日：2007-05-22
申请号：US10959253
申请日：2004-10-04
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： H01L27/01 , H01L10/20
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0688 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.
摘要翻译：本发明包括具有与晶体管器件的源/漏区电连接的薄膜叠层电阻器的半导体结构。电阻器包括可以彼此或可以彼此不同的第一和第二晶体层。第一和第二结晶层中的一个包括掺杂的硅/锗，另一个包括掺杂的硅。晶体管器件和电阻器可以是形成在常规衬底（例如单晶硅晶片）或非常规衬底（诸如玻璃，氧化铝，二氧化硅，金属和塑料中的一种或多种）的SOI结构的一部分，。本发明还包括形成半导体结构的方法，并且在具体方面，包括形成电阻器结构的工艺。

40. 发明申请

US20070047319A1 Scalable flash/NV structures and devices with extended endurance 审中-公开
标题翻译：可扩展闪存/ NV结构和延长耐用性的设备
公开(公告)号：US20070047319A1
公开(公告)日：2007-03-01
申请号：US11592779
申请日：2006-11-03
申请人： Arup Bhattacharyya
发明人： Arup Bhattacharyya
IPC分类号： G11C11/34
CPC分类号： H01L21/28194 , B82Y10/00 , G11C16/0416 , G11C16/0466 , G11C2216/06 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to an embodiment of a method for operating a nonvolatile memory device, one or more non-volatile memory cells in one or more arrays are written by applying a voltage across a dielectric to store charge on charge centers in the high K dielectric, and one or more non-volatile memory cells are erased by applying a voltage across the dielectric to tunnel electrons off of the charge centers. Applying a voltage across a dielectric includes enhancing a resulting electric field using an injector medium and a high K dielectric. Other aspects and embodiments are provided herein.
摘要翻译：根据用于操作非易失性存储器件的方法的实施例，通过在电介质上施加电压来写入一个或多个阵列中的一个或多个非易失性存储单元，以在高K电介质中的电荷中心上存储电荷，并且一个或更多的非易失性存储单元通过在电介质上施加电压来将电子从电荷中心隧道引出而被擦除。在电介质上施加电压包括使用注射介质和高K电介质增强所得到的电场。本文提供了其它方面和实施例。

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