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31. 发明授权

US08350375B2 Flipchip bump patterns for efficient I-mesh power distribution schemes 有权
标题翻译： Flipchip凸点图案用于高效的I网格配电方案
公开(公告)号：US08350375B2
公开(公告)日：2013-01-08
申请号：US12121363
申请日：2008-05-15
申请人： Anwar Ali , Kalyan Doddapaneni , Wilson Leung
发明人： Anwar Ali , Kalyan Doddapaneni , Wilson Leung
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/5286 , H01L24/13 , H01L2224/16 , H01L2924/01077 , H01L2924/01079 , H01L2924/30107
摘要： Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.
摘要翻译：公开了一种倒装芯片方案，其中电源和接地凸块以条纹配置布置。具体地说，存在多条电源凸块和多条接地凸块。每条电源凸块通过网状电源总线相互连接，每条接地凸块通过网状接地母线互连。总线在凸块之间短路，而不必使用金属接头延长线。这种布置规定：可以在凸起线之间提供信号路由; 和/或网状芯功率总线可以提供为更宽以便提供改进的功率网格性能和/或为了减少或消除第二最顶层金属层上所需的金属。

32. 发明申请

US20090283904A1 FLIPCHIP BUMP PATTERNS FOR EFFICIENT I-MESH POWER DISTRIBUTION SCHEMES 有权
标题翻译： FLIPCHIP BUMP PATTERNS有效的I-MESH功率分配方案
公开(公告)号：US20090283904A1
公开(公告)日：2009-11-19
申请号：US12121363
申请日：2008-05-15
申请人： Anwar Ali , Kalyan Doddapaneni , Wilson Leung
发明人： Anwar Ali , Kalyan Doddapaneni , Wilson Leung
IPC分类号： H01L23/48
CPC分类号： H01L23/5286 , H01L24/13 , H01L2224/16 , H01L2924/01077 , H01L2924/01079 , H01L2924/30107
摘要： Disclosed is a flipchip scheme where power and ground bumps are arranged in a striped configuration. Specifically, there are a plurality of lines of power bumps, and a plurality of lines of ground bumps. Each line of power bumps is interconnected by a mesh core power bus, and each line of ground bumps is interconnected by a mesh core ground bus. The busses are shorted across the bumps without having to use metal tab extensions. This arrangement provides that: signal routing can be provided between the lines of bumps; and/or the mesh core power busses can be provided as being wider in order to provide improved power mesh performance and/or in order to reduce or eliminate the metal required on the second top-most metal layer.
摘要翻译：公开了一种倒装芯片方案，其中电源和接地凸块以条纹配置布置。具体地说，存在多条电源凸块和多条接地凸块。每条电源凸块通过网状电源总线相互连接，每条接地凸块通过网状接地母线互连。总线在凸块之间短路，而不必使用金属接头延长线。这种布置规定：可以在凸起线之间提供信号路由; 和/或网状芯功率总线可以提供为更宽以便提供改进的功率网格性能和/或为了减少或消除第二最顶层金属层上所需的金属。

33. 发明申请

US20090160475A1 Test pin reduction using package center ball grid array 审中-公开
标题翻译：使用封装中心球栅阵列测试引脚减少
公开(公告)号：US20090160475A1
公开(公告)日：2009-06-25
申请号：US12004131
申请日：2007-12-20
申请人： Anwar Ali , Thinh Tran , Wilson Choi
发明人： Anwar Ali , Thinh Tran , Wilson Choi
IPC分类号： G01R31/26 , G06F17/50
CPC分类号： G01R31/2884 , G06F2217/40 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L2224/16225
摘要： An apparatus and method for reducing the number of package pins in a chip package which must be budgeted for test purposes. In one embodiment, the invention achieves this by housing test balls in the depopulated center of a package ball array. The test balls are used to test a chip package prior to connection with a printed wiring board (PWB)/printed circuit board (PCB). After tests are completed, and when the chip package is connected to a PWB/PCB, the test balls may be left electrically isolated and unconnected. In another embodiment, the test balls are located in previously unused interstitial sites in a package ball array.
摘要翻译：一种用于减少芯片封装中的封装引脚数量的装置和方法，其必须用于测试目的。在一个实施例中，本发明通过将测试球容纳在包装球阵列的减排中心来实现。测试球用于在与印刷电路板（PWB）/印刷电路板（PCB）连接之前测试芯片封装。测试完成后，当芯片封装连接到PWB / PCB时，测试球可能会被电隔离和未连接。在另一个实施例中，测试球位于包装球阵列中的先前未使用的间隙位置。

34. 发明授权

US07430730B2 Disabling unused IO resources in platform-based integrated circuits 失效
标题翻译：在基于平台的集成电路中禁用未使用的IO资源
公开(公告)号：US07430730B2
公开(公告)日：2008-09-30
申请号：US10909603
申请日：2004-08-02
申请人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
发明人： Anwar Ali , Julie Beatty , Kalyan Doddapaneni
IPC分类号： G06F17/50
CPC分类号： G01R31/31712 , G01R31/31704
摘要： The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
摘要翻译：本发明涉及用于在基于平台的集成电路中禁用未使用的IO资源的方法。从供应商接收到一个切片。该片包括客户未使用的IO电路。 IO电路被禁止。例如，当IO电路需要连接到电源时，IO电路的主输入/输出引脚与IO电路的电源总线短路。当IO电路需要连接到接地源时，IO电路的主输入/输出引脚短接到IO电路的接地总线。当IO电路需要悬浮时，IO电路的主输入/输出引脚不连接到片的任何焊盘单元。接下来，IO电路从客户的逻辑设计网表中删除。 IO电路插入供应商的物理设计数据库。

35. 发明申请

US20060027919A1 Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuits 有权
标题翻译：通过阵列和互连进行尺寸调整以减少倒装芯片集成电路中的布线拥塞的方法
公开(公告)号：US20060027919A1
公开(公告)日：2006-02-09
申请号：US10914657
申请日：2004-08-09
申请人： Anwar Ali , Wei Huang
发明人： Anwar Ali , Wei Huang
IPC分类号： G06F17/50 , H01L23/48
CPC分类号： H01L24/11 , H01L21/76816 , H01L21/76838 , H01L23/5226 , H01L2224/13099 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/30105 , H01L2924/30107 , H01L2224/0401
摘要： A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.
摘要翻译：公开了一种用于减少集成电路设计中的路由拥塞的方法和计算机程序，其包括以下步骤：（a）作为输入接收具有内部金属层和顶部金属层的集成电路管芯的设计，其中该设计包括电气约束在所述集成电路管芯中的多个I / O电路中的每一个; （b）选择多个用于通孔阵列的通孔，以形成集成电路管芯的内金属层和顶金属层之间的电连接，该电连接将形成在顶部金属层上的焊料凸块与多个相应的一个形成的I / O电路，其中选择通孔的数量以满足多个I / O电路中的相应一个的电气约束; 和（c）产生为通孔阵列确定的通孔的数量。

36. 发明申请

US20050125759A1 Cell-based method for creating slotted metal in semiconductor designs 有权
标题翻译：用于在半导体设计中创建开槽金属的基于单元的方法
公开(公告)号：US20050125759A1
公开(公告)日：2005-06-09
申请号：US10732395
申请日：2003-12-09
申请人： Anwar Ali , Tauman Lau , Kalyan Doddapaneni
发明人： Anwar Ali , Tauman Lau , Kalyan Doddapaneni
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G06F17/5068 , H01L27/0203
摘要： A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.
摘要翻译：公开了一种用于在半导体设计中产生开槽金属结构的计算机实现的方法。本发明的方面包括提供不同类型的预开槽构件块元件的库。此后，在芯片设计期间，从库中选择多个元件并将其放置在邻接的设计中以形成复合开槽金属结构。

37. 发明授权

US06591410B1 Six-to-one signal/power ratio bump and trace pattern for flip chip design 有权
标题翻译：用于倒装芯片设计的六对一信号/功率比凸块和迹线图案
公开(公告)号：US06591410B1
公开(公告)日：2003-07-08
申请号：US09752626
申请日：2000-12-28
申请人： Anwar Ali , Mike Teh-An Liang , Bing Yi
发明人： Anwar Ali , Mike Teh-An Liang , Bing Yi
IPC分类号： G06F1750
CPC分类号： H01L23/50 , G06F17/5068 , H01L2924/0002 , H01L2924/15173 , H01L2924/00
摘要： A method for making a bump and trace layout for an integrated circuit die includes the step of replicating a routing tile having a first column of I/O pads and a second column of I/O pads wherein the first column is offset from the second column so that the I/O pads of the first column are interleaved between the I/O pads of the second column.
摘要翻译：一种用于制造用于集成电路管芯的突起和迹线布局的方法包括复制具有第一列I / O焊盘和第二列I / O焊盘的布线板的步骤，其中第一列偏离第二列使得第一列的I / O焊盘交错在第二列的I / O焊盘之间。

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