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31. 发明授权

US08008151B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US08008151B2
公开(公告)日：2011-08-30
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

32. 发明授权

US07767526B1 High density trench MOSFET with single mask pre-defined gate and contact trenches 有权
标题翻译：具有单掩模预定义栅极和接触沟槽的高密度沟槽MOSFET
公开(公告)号：US07767526B1
公开(公告)日：2010-08-03
申请号：US12362414
申请日：2009-01-29
申请人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
发明人： Yeeheng Lee , Hong Chang , Tiesheng Li , John Chen , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L21/26586 , H01L29/4236 , H01L29/78
摘要： Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches that are wider than those trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact.
摘要翻译：沟槽栅极MOSFET器件可以使用单个掩模形成以限定栅极沟槽和主体接触沟槽。在半导体基板的表面上形成硬掩模。在硬掩模上施加沟槽掩模以预定义接触沟槽和栅极沟槽。这些预定沟槽同时被蚀刻到衬底中到达第一预定深度。接下来将栅极沟槽掩模施加在硬掩模的顶部上。栅极沟槽掩模覆盖主体接触沟槽，并且在栅极沟槽处具有比那些沟槽更宽的开口。栅极沟槽而不是体接触沟槽被蚀刻到第二预定深度。第一种导电材料可以填充栅沟以形成栅极。第二种导电材料可以填充身体接触沟槽以形成身体接触。

33. 发明授权

US07605425B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07605425B2
公开(公告)日：2009-10-20
申请号：US11900616
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。

34. 发明申请

US20080090357A1 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US20080090357A1
公开(公告)日：2008-04-17
申请号：US11983769
申请日：2007-11-09
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate, through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate structure that extends substantially above the top substrate surface.
摘要翻译：一种制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成通过硬掩模的沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部衬底表面，并且去除硬掩模以留下基本上在顶部衬底表面上方延伸的栅极结构。

35. 发明申请

US20120001176A1 ETCH DEPTH DETERMINATION STRUCTURE 有权
标题翻译： ETCH深度测定结构
公开(公告)号：US20120001176A1
公开(公告)日：2012-01-05
申请号：US13231872
申请日：2011-09-13
申请人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
发明人： Yingying Lou , Tiesheng Li , Yu Wang , Anup Bhalla
IPC分类号： H01L23/544
CPC分类号： H01L22/12 , H01L29/407 , H01L29/66734 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device wafer includes a test structure. The test structure includes a layer of material having an angle-shaped test portion disposed on at least a portion of a surface of the semiconductor wafer. A ruler marking on the surface of the semiconductor wafer proximate the test portion is adapted to facilitate measurement of a change in length of the test portion.
摘要翻译：半导体器件晶片包括测试结构。测试结构包括具有设置在半导体晶片的表面的至少一部分上的角形测试部分的材料层。在靠近测试部分的标记在半导体晶片的表面上的标尺适于便于测量测试部分的长度变化。

36. 发明授权

US07875541B2 Shallow source MOSFET 有权
标题翻译：浅源MOSFET
公开(公告)号：US07875541B2
公开(公告)日：2011-01-25
申请号：US12655162
申请日：2009-12-22
申请人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
发明人： Sung-Shan Tai , Tiesheng Li , Anup Bhalla , Hong Chang , Moses Ho
IPC分类号： H01L21/3205
CPC分类号： H01L29/7813 , H01L29/456 , H01L29/4933 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： Fabricating a semiconductor device includes forming a hard mask on a substrate having a top substrate surface, forming a trench in the substrate through the hard mask, depositing gate material in the trench, where the amount of gate material deposited in the trench extends beyond the top substrate surface, and removing the hard mask to leave a gate having a gate top surface that extends substantially above the top substrate surface at least in center region of the trench opening, the gate having a vertical edge that includes an extended portion, the extended portion extending above the trench opening and being substantially aligned with the trench wall. It further includes implanting a body, implanting a plurality of source regions embedded in the body, forming a plurality of spacers that insulate the source regions from the gate, the plurality of spacers being situated immediately adjacent to the gate and immediately adjacent to respective ones of the plurality of source regions, wherein the plurality of spacers do not substantially extend into the trench and do not substantially extend over the trench, disposing a dielectric layer over the source, the spacers, the gate, and at least a portion of the body, forming a contact opening, and disposing metal to form a contact with the body at the contact opening.
摘要翻译：制造半导体器件包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中通过硬掩模形成沟槽，在沟槽中沉积栅极材料，其中沉积在沟槽中的栅极材料的量延伸超过顶部并且去除硬掩模以离开具有栅极顶表面的栅极，该栅极顶表面至少在沟槽开口的中心区域基本上在顶部衬底表面上方延伸，栅极具有包括延伸部分的垂直边缘，延伸部分延伸到沟槽开口之上并与沟槽壁基本对齐。它还包括植入物体，植入嵌入在体内的多个源区，形成多个间隔物，使得源极区域与栅极绝缘，多个间隔物紧邻栅极并且紧邻栅极所述多个源极区域，其中所述多个间隔物基本上不延伸到所述沟槽中并且基本上不延伸穿过所述沟槽，在所述源极，所述间隔物，所述栅极以及所述主体的至少一部分之上设置介电层，形成接触开口，并且在接触开口处设置金属以与身体形成接触。

37. 发明授权

US07800169B2 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US07800169B2
公开(公告)日：2010-09-21
申请号：US11900603
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

38. 发明授权

US07521332B2 Resistance-based etch depth determination for SGT technology 有权
标题翻译： SGT技术的电阻蚀刻深度测定
公开(公告)号：US07521332B2
公开(公告)日：2009-04-21
申请号：US11690581
申请日：2007-03-23
申请人： Tiesheng Li , Yu Wang , Yingying Lou , Anup Bhalla
发明人： Tiesheng Li , Yu Wang , Yingying Lou , Anup Bhalla
IPC分类号： H01L21/76
CPC分类号： H01L22/34 , H01L22/12 , H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut DL of the test structure is determined from the signal and an etch depth DT is determined from DL. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.
摘要翻译：公开了一种用于确定深度蚀刻的方法，形成屏蔽栅沟槽（SGT）结构的方法和半导体器件晶片。在具有沟槽的衬底的一部分上形成材料层。材料填充沟槽。将抗蚀剂掩模放置在材料层的测试部分上，从而限定位于抗蚀剂掩模下方的测试结构。抗蚀剂掩模不覆盖沟槽。该材料被各向同性地蚀刻并且测量与测试结构的电阻变化相关的信号。从信号确定测试结构的横向底切DL，并且从DL确定蚀刻深度DT。晶片可以包括形成桥接电路的一个或多个测试结构; 通过接触孔将测试结构电连接的一个或多个金属触点和包括在测试结构上的抗蚀剂层。

39. 发明申请

US20080001220A1 Power MOS device 有权
标题翻译：功率MOS器件
公开(公告)号：US20080001220A1
公开(公告)日：2008-01-03
申请号：US11900616
申请日：2007-09-11
申请人： Anup Bhalla , Sik Lui , Tiesheng Li
发明人： Anup Bhalla , Sik Lui , Tiesheng Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/4236 , H01L29/456 , H01L29/47 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811
摘要： A semiconductor device comprises a drain, a body disposed over the drain, having a body top surface, a source embedded in the body, extending downward from the body top surface into the body, a gate trench extending through the source and the body into the drain, a gate disposed in the gate trench, a source body contact trench having a trench wall and an anti-punch through implant that is disposed along the trench wall. A method of fabricating a semiconductor device comprises forming a hard mask on a substrate having a top substrate surface, forming a gate trench in the substrate, through the hard mask, depositing gate material in the gate trench, removing the hard mask to leave a gate structure, forming a source body contact trench having a trench wall and forming an anti-punch through implant.
摘要翻译：半导体器件包括漏极，设置在漏极上的主体，具有主体顶表面，嵌入在主体中的源，从主体顶表面向下延伸到主体中;延伸穿过源和主体的栅沟槽，漏极，设置在栅极沟槽中的栅极，具有沟槽壁的源体接触沟槽和沿着沟槽壁布置的抗穿孔植入物。制造半导体器件的方法包括在具有顶部衬底表面的衬底上形成硬掩模，在衬底中形成栅极沟槽，通过硬掩模，在栅极沟槽中沉积栅极材料，去除硬掩模以留下栅极形成具有沟槽壁并形成抗穿孔植入物的源体接触沟槽。

40. 发明授权

US08735968B2 Integrated MOSFET devices with Schottky diodes and associated methods of manufacturing 有权
标题翻译：具有肖特基二极管和相关制造方法的集成MOSFET器件
公开(公告)号：US08735968B2
公开(公告)日：2014-05-27
申请号：US12980143
申请日：2010-12-28
申请人： Tiesheng Li , Lei Zhang
发明人： Tiesheng Li , Lei Zhang
IPC分类号： H01L27/105 , H01L21/8234
CPC分类号： H01L29/7811 , H01L27/0629 , H01L29/0619 , H01L29/0696 , H01L29/41766 , H01L29/7806 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： The present technology discloses a semiconductor die integrating a MOSFET device and a Schottky diode. The semiconductor die comprises a MOSFET area comprising the active region of MOSFET, a Schottky diode area comprising the active region of Schottky diode, and a termination area comprising termination structures. Wherein the Schottky diode area is placed between the MOSFET area and the termination area such that the Schottky diode area surrounds the MOSFET area.
摘要翻译：本技术公开了一种集成MOSFET器件和肖特基二极管的半导体管芯。半导体管芯包括MOSFET区域，其包括MOSFET的有源区，包括肖特基二极管的有源区的肖特基二极管区域和包含端接结构的终端区域。其中肖特基二极管区域放置在MOSFET区域和端接区域之间，使得肖特基二极管区域围绕MOSFET区域。

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