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    • 31. 发明授权
    • Geometrically efficient self-inflating seat cushion
    • 几何效能自充气座垫
    • US5469592A
    • 1995-11-28
    • US126552
    • 1993-09-27
    • Mark C. Johnson
    • Mark C. Johnson
    • A47C27/08
    • A47C27/088A47C27/084A47C27/18Y10S297/03
    • A self-inflating seat cushion is shown with airtight hollow body 32 comprising flexible material and resilient structure member 30 comprising foam. Hollow, resilient structure member 30, made of flat portions of material, can lie on the inside or attach to the outside of airtight hollow body 32. During inflating, resilient structure member 30 expands moving airtight hollow body 32 into an arching configuration with high volume relative to its dimensions. A proportionate volume of air flows into the chamber. During use, the chamber flattens and deforms, airtight hollow body 32's volume diminishes, its internal pressure increases proportionately, and the seat cushions and supports weight.
    • 自充气座垫被示出为具有气密的中空体32,其包括柔性材料和包含泡沫的弹性结构构件30。 由材料的平坦部分制成的中空的弹性结构件30可以位于内部或附着到气密中空本体32的外部。在充气过程中,弹性结构件30将移动的气密中空本体32膨胀成具有高体积的拱形构型 相对于其尺寸。 一定比例的空气流入室内。 在使用过程中,气室平坦变形,气密中空体32的体积减小,其内部压力成比例地增加,座垫和支撑件重量增加。
    • 32. 发明授权
    • Integrated cross-tester analysis and real-time adaptive test
    • 集成交叉测试仪分析和实时自适应测试
    • US08862424B2
    • 2014-10-14
    • US13603892
    • 2012-09-05
    • Mark C. JohnsonDeepak S. TuragaOlivier Verscheure
    • Mark C. JohnsonDeepak S. TuragaOlivier Verscheure
    • G01D3/00G01P21/00G01R31/28G01R31/319
    • G01R31/31901G01R31/2894G01R31/3191
    • Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.
    • 通过在自适应测试引擎分析每个测试结果来处理来自多个单独的半导体测试器的测试结果。 集中式系统共同分析来自多个单独的半导体测试器的所有测试结果。 自适应测试引擎或集中式系统基于对每个测试结果的分析或所有测试结果的联合分析来识别以下一个或多个:测试环境问题,测试者变异性问题,测试仪校准问题,产品 变异性问题和制造过程变异性问题。 自适应测试引擎或集中式系统确定多个单独半导体测试仪中的一个或多个是否导致所识别的一个或多个问题,或者由多个单独的半导体测试仪测试的半导体产品是否导致所识别的一个或多个问题。
    • 33. 发明申请
    • INTEGRATED CROSS-TESTER ANALYSIS AND REAL-TIME ADAPTIVE TEST
    • 综合交叉测试分析和实时自适应测试
    • US20120330593A1
    • 2012-12-27
    • US13603892
    • 2012-09-05
    • Mark C. JohnsonDeepak S. TuragaOlivier Verscheure
    • Mark C. JohnsonDeepak S. TuragaOlivier Verscheure
    • G01R31/26G01R35/00G06F19/00
    • G01R31/31901G01R31/2894G01R31/3191
    • Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.
    • 通过在自适应测试引擎分析每个测试结果来处理来自多个单独的半导体测试器的测试结果。 集中式系统共同分析来自多个单独的半导体测试器的所有测试结果。 自适应测试引擎或集中式系统基于对每个测试结果的分析或所有测试结果的联合分析来识别以下一个或多个:测试环境问题,测试者变异性问题,测试仪校准问题,产品 变异性问题和制造过程变异性问题。 自适应测试引擎或集中式系统确定多个单独半导体测试仪中的一个或多个是否导致所识别的一个或多个问题,或者由多个单独的半导体测试仪测试的半导体产品是否导致所识别的一个或多个问题。
    • 35. 发明授权
    • Apparatus, system, and method for managing errors in prefetched data
    • 用于管理预取数据中的错误的装置,系统和方法
    • US07437593B2
    • 2008-10-14
    • US10619816
    • 2003-07-14
    • Mark C. JohnsonBitwoded OkbayAndrew MoyLih-Chung Kuo
    • Mark C. JohnsonBitwoded OkbayAndrew MoyLih-Chung Kuo
    • G06F11/00
    • G06F11/1008
    • An apparatus, system, and method are provided for managing errors in prefetched data. The apparatus, system, and method identify prefetched data that contains an uncorrectable error. In addition, the apparatus, system, and method initiate an error recovery process only for prefetched data that is actually used by a requesting device, module, or application. The apparatus includes a prefetch module that prefetches data packets, a validation module that determines whether a prefetched data packet contains an uncorrectable error, a transfer module that transfers prefetched data packets to a requester, and an error recovery module that selectively initiates error recovery for those data packets that contain an uncorrectable error and are actually transferred to the requester.
    • 提供了一种用于管理预取数据中的错误的装置,系统和方法。 装置,系统和方法识别包含不可校正错误的预取数据。 此外,装置,系统和方法仅针对由请求的设备,模块或应用实际使用的预取数据启动错误恢复过程。 该装置包括预取数据分组的预取模块,确定预取数据分组是否包含不可校正错误的确认模块,将预取数据分组传送到请求者的传输模块,以及为那些选择性地启动错误恢复的错误恢复模块 数据包包含不可纠正的错误,实际上传输到请求者。
    • 36. 发明申请
    • SYSTEMS AND METHODS FOR VERIFYING RECOVERY FROM AN INTERMITTENT HARDWARE FAULT
    • 用于从间歇性硬件故障中验证恢复的系统和方法
    • US20080239942A1
    • 2008-10-02
    • US11693206
    • 2007-03-29
    • Joe S. HsuMark C. JohnsonHugh W. McDevitt
    • Joe S. HsuMark C. JohnsonHugh W. McDevitt
    • G01R31/08
    • G06F11/26
    • Systems and methods for verifying recovery from intermittent hardware faults. Exemplary embodiments include a method for verifying recovery from intermittent hardware faults, the method including generating an error in a computer interface by forcing a hardware fault after setting an error injection enable control bit in a register coupled to the computer interface, detecting an error in a hardware checker coupled to the computer interface which asserts an error interrupt signal resetting the error injection enable control bit when the error interrupt signal and a hardware reset control bit coupled to the computer interface are both active, disabling error forcing when the error injection enable control bit is reset, and executing an error recovery and logging procedure in the computer interface.
    • 用于验证从间歇性硬件故障中恢复的系统和方法。 示例性实施例包括用于验证来自间歇性硬件故障的恢复的方法,所述方法包括在将耦合到计算机接口的寄存器中设置错误注入使能控制位之后强制硬件故障在计算机接口中产生错误,检测到 硬件检查器耦合到计算机接口,当错误中断信号和耦合到计算机接口的硬件复位控制位均为活动时,断言错误中断信号复位错误注入使能控制位,当错误注入使能控制位 被重置,并在计算机接口中执行错误恢复和记录过程。
    • 39. 发明授权
    • Memory controller for reading data from synchronous RAM
    • 用于从同步RAM读取数据的存储器控​​制器
    • US5577236A
    • 1996-11-19
    • US367514
    • 1994-12-30
    • Mark C. JohnsonDonald J. LangSudha SarmaForrest L. WadeAdalberto G. Yanes
    • Mark C. JohnsonDonald J. LangSudha SarmaForrest L. WadeAdalberto G. Yanes
    • G06F13/16G11C7/10G06F12/00
    • G11C7/222G06F13/1689G11C7/1072
    • A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have. If desired, an additional, user-selectable supplementary delay unit may be used to increase the delay provided by the delay module, thereby increasing or offsetting the delay of the selected sampling clock signal. The delay module provides a delayed clock signal to synchronize receipt of Read data signals from the memory bank at a clocked latch, enabling the latch to receive the Read data signals during the appropriate data valid window. Specifically, the latch is activated by receipt of Read command signals, which may be coordinated, for example, with the rising edge of the delayed clock signal. The latched Read data signals are then available for use by other logic circuitry.
    • 存储器控制器通过补偿由存储器加载,芯片和卡制造过程变化等导致的数据的延迟,从而在小且可变的数据有效窗口期间从同步RAM的存储体读取数据。 存储器控制器包括用于向存储体提供时钟参考信号的系统时钟驱动器。 采样时钟提供与系统时钟信号重复的各种采样时钟信号,具有各种延迟。 命令驱动程序通过将Read命令信号中继到存储体来启动存储体中的Read操作。 响应于诸如存储器组中存在的存储器模块的数量的存储器加载的级别,时钟选择器将选择的一个采样时钟信号引导到延迟模块,延迟模块复制系统时钟驱动器可能具有的任何延迟。 如果需要,可以使用附加的用户可选择的辅助延迟单元来增加由延迟模块提供的延迟,从而增加或抵消所选择的采样时钟信号的延迟。 延迟模块提供延迟的时钟信号,以在时钟锁存器上同步来自存储体的读取数据信号的接收,使得锁存器能够在适当的数据有效窗口期间接收读取数据信号。 具体地,锁存器通过接收可以例如与延迟的时钟信号的上升沿协调的读命令信号来激活。 锁存的读数据信号可供其他逻辑电路使用。
    • 40. 发明授权
    • Laminated finger seal with logarithmic curvature
    • 具有对数曲率的层压手指密封
    • US5108116A
    • 1992-04-28
    • US708150
    • 1991-05-31
    • Mark C. JohnsonEric G. Medlin
    • Mark C. JohnsonEric G. Medlin
    • F16J15/32
    • F16J15/3288
    • An annular sealing apparatus comprised of at least a pair of axially stacked thin diaphragm members is provided. Each of diaphragm members includes a planar array of radially extending fingers separated by gaps. The fingers have a logarithmic curvature as they extend from their innermost end to their outermost end. The fingers also have a constant thickness along their length and also have a foot integral with their innermost end. This foot is wider than the fingers and thereby provides a larger wear surface. The pair of diaphragm members are disposed so that the fingers of each block the gaps of the other.
    • 提供了由至少一对轴向层叠的薄隔膜构件构成的环形密封装置。 每个隔膜构件包括由间隙分开的径向延伸的手指的平面阵列。 手指从最内端延伸到最外端时具有对数曲率。 手指沿其长度也具有恒定的厚度,并且还具有与其最内端一体的脚。 该脚比手指宽,从而提供更大的磨损表面。 这对隔膜部件设置成使得每个隔膜部件的指状物阻挡另一个的间隙。