专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US08901537B2 Transistors with high concentration of boron doped germanium 有权
标题翻译：具有高浓度硼掺杂锗的晶体管
公开(公告)号：US08901537B2
公开(公告)日：2014-12-02
申请号：US12975278
申请日：2010-12-21
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L21/285 , H01L29/165 , H01L29/167 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/45
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

32. 发明申请

US20150060945A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20150060945A1
公开(公告)日：2015-03-05
申请号：US14535387
申请日：2014-11-07
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/36 , H01L21/02 , H01L29/78 , H01L29/66 , H01L29/165 , H01L29/08
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

33. 发明申请

US20120153387A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 有权
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20120153387A1
公开(公告)日：2012-06-21
申请号：US12975278
申请日：2010-12-21
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

34. 发明申请

US20090152589A1 Systems And Methods To Increase Uniaxial Compressive Stress In Tri-Gate Transistors 审中-公开
标题翻译：在三栅晶体管中提高单轴压缩应力的系统和方法
公开(公告)号：US20090152589A1
公开(公告)日：2009-06-18
申请号：US11958275
申请日：2007-12-17
申请人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
发明人： Titash Rakshit , Martin D. Giles , Tahir Ghani , Anand Murthy , Stephen M. Cea
IPC分类号： H01L29/778 , H01L21/8234
CPC分类号： H01L21/26506 , H01L21/823437 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A transistor structure that increases uniaxial compressive stress on the channel region of a tri-gate transistor comprises at least two semiconductor bodies formed on a substrate, each semiconductor body having a pair of laterally opposite sidewalls and a top surface, a common source region formed on one end of the semiconductor bodies, wherein the common source region is coupled to all of the at least two semiconductor bodies, a common drain region formed on another end of the semiconductor bodies, wherein the common drain region is coupled to all of the at least two semiconductor bodies, and a common gate electrode formed over the at least two semiconductor bodies, wherein the common gate electrode provides a gate electrode for each of the at least two semiconductor bodies and wherein the common gate electrode has a pair of laterally opposite sidewalls that are substantially perpendicular to the sidewalls of the semiconductor bodies.
摘要翻译：增加三栅极晶体管的沟道区上的单轴压应力的晶体管结构包括形成在衬底上的至少两个半导体本体，每个半导体本体具有一对横向相对的侧壁和顶表面，共同源极区形成在所述半导体主体的一端，其中所述公共源极区域耦合到所述至少两个半导体主体中的所有半导体主体，形成在所述半导体主体的另一端上的公共漏极区域，其中，所述公共漏极区域至少与所述半导体主体两个半导体主体和形成在所述至少两个半导体主体上的公共栅电极，其中所述公共栅电极为所述至少两个半导体主体中的每一个提供栅电极，并且其中所述公共栅极具有一对横向相对的侧壁，基本上垂直于半导体主体的侧壁。

35. 发明申请

US20080242037A1 Semiconductor device having self-aligned epitaxial source and drain extensions 有权
标题翻译：具有自对准外延源极和漏极延伸部分的半导体器件
公开(公告)号：US20080242037A1
公开(公告)日：2008-10-02
申请号：US11729189
申请日：2007-03-28
申请人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
发明人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
摘要翻译：一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料基质。

36. 发明授权

US07732285B2 Semiconductor device having self-aligned epitaxial source and drain extensions 有权
标题翻译：具有自对准外延源极和漏极延伸部分的半导体器件
公开(公告)号：US07732285B2
公开(公告)日：2010-06-08
申请号：US11729189
申请日：2007-03-28
申请人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
发明人： Bernhard Sell , Tahir Ghani , Anand Murthy , Harry Gomez
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26513 , H01L21/30608 , H01L21/3065 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate.
摘要翻译：一种形成具有在晶体管的栅介质层附近的具有自对准源极和漏极延伸部分的晶体管的方法包括在衬底上形成栅极堆叠，将掺杂剂注入到与栅极堆叠相邻的衬底区域中，其中掺杂剂增加了衬底的蚀刻速率并且限定了源极和漏极延伸部分的位置，在栅堆叠的横向相对侧上形成一对间隔物，该衬垫设置在衬底的掺杂区域的顶部，蚀刻衬底的掺杂区域以及所述衬底的与所述掺杂区域相邻的部分，其中所述掺杂区域的蚀刻速率高于所述衬底的与所述掺杂区域相邻的部分的蚀刻速率，以及在所述掺杂区域的蚀刻部分中沉积硅基材料基质。

37. 发明授权

US09728464B2 Self-aligned 3-D epitaxial structures for MOS device fabrication 有权
公开(公告)号：US09728464B2
公开(公告)日：2017-08-08
申请号：US13560513
申请日：2012-07-27
申请人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Tahir Ghani
发明人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Tahir Ghani
IPC分类号： H01L21/335 , H01L21/8238 , H01L29/10
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

38. 发明申请

US20150171218A1 MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS 有权
标题翻译：多电压电压器件及相关技术及配置
公开(公告)号：US20150171218A1
公开(公告)日：2015-06-18
申请号：US14108265
申请日：2013-12-16
申请人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
发明人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/28114 , H01L21/823431 , H01L21/82345 , H01L21/823456 , H01L27/0886 , H01L29/42372 , H01L29/42376 , H01L29/4908 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66484 , H01L29/66772 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/78645
摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了多阈值电压装置及相关联的技术和配置。在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中，第一厚度大于第二厚度。可以描述和/或要求保护其他实施例。

39. 发明申请

US20140264679A1 LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS 有权
标题翻译：逻辑芯片，包括嵌入式磁性隧道结
公开(公告)号：US20140264679A1
公开(公告)日：2014-09-18
申请号：US13994716
申请日：2013-03-15
申请人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01L27/222 , H01L27/226 , H01L43/08
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
摘要翻译：实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。在一个实施例中，第一和第二ILD直接彼此接触。本文描述了其它实施例。

40. 发明申请

US20140191300A1 HARD MASK ETCH STOP FOR TALL FINS 有权
标题翻译：硬盘防火墙防火墙
公开(公告)号：US20140191300A1
公开(公告)日：2014-07-10
申请号：US13997161
申请日：2011-12-31
申请人： Ritesh Jhaveri , Bernard Sell , Tahir Ghani
发明人： Ritesh Jhaveri , Bernard Sell , Tahir Ghani
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/0638 , H01L21/823431 , H01L21/823821 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
摘要翻译：在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度，并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模在鳍的顶表面上的蚀刻停止层。去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式