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31. 发明授权

US07916523B2 Method of erasing a resistive memory device 有权
标题翻译：擦除电阻式存储器件的方法
公开(公告)号：US07916523B2
公开(公告)日：2011-03-29
申请号：US11633941
申请日：2006-12-05
申请人： An Chen , Sameer Haddad , Yi-Ching Jean Wu , Swaroop Kaza
发明人： An Chen , Sameer Haddad , Yi-Ching Jean Wu , Swaroop Kaza
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0007 , G11C13/0097 , G11C2013/0071 , G11C2213/32 , G11C2213/72 , G11C2213/79
摘要： In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.
摘要翻译：在擦除电阻式存储器件的第一种方法中，将电位施加到与电阻性存储器件串联的晶体管的栅极，并且通过电阻存储器件提供连续增加的电流，通过提供连续增加的电势跨越电阻式存储器件。在擦除电阻性存储器件的第二种方法中，电阻被施加在电阻存储器件两端，并且通过电阻存储器件提供连续增加的电流，通过向晶体管的栅极串联提供连续增加的电势，电阻式存储器件。

32. 发明授权

US07706168B2 Erase, programming and leakage characteristics of a resistive memory device 有权
标题翻译：电阻式存储器件的擦除，编程和漏电特性
公开(公告)号：US07706168B2
公开(公告)日：2010-04-27
申请号：US11980116
申请日：2007-10-30
申请人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
发明人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
摘要翻译：本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。

33. 发明申请

US20090109727A1 Erase, programming and leakage characteristics of a resistive memory device 有权
标题翻译：电阻式存储器件的擦除，编程和漏电特性
公开(公告)号：US20090109727A1
公开(公告)日：2009-04-30
申请号：US11980116
申请日：2007-10-30
申请人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
发明人： Tzu-Ning Fang , Steven Avanzino , Swaroop Kaza , Dongxiang Liao , Christie Marrian , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/32 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： The present method provides annealing of a resistive memory device so as to provide that the device in its erased state has a greatly increased resistance as compared to a prior art approach. The annealing also provides that the device may be erased by application of any of a plurality of electrical potentials within an increased range of electrical potentials as compared to the prior art.
摘要翻译：本方法提供了电阻式存储器件的退火，从而使得与现有技术方法相比，处于其擦除状态的器件具有大大增加的电阻。退火还规定，与现有技术相比，可以在增加的电位范围内通过施加多个电位中的任何一个来擦除器件。

34. 发明申请

US20090072234A1 Test Stuctures for development of metal-insulator-metal (MIM) devices 有权
标题翻译：金属绝缘体金属（MIM）器件开发的测试结构
公开(公告)号：US20090072234A1
公开(公告)日：2009-03-19
申请号：US12313089
申请日：2008-11-17
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.
摘要翻译：在本发明的电子测试结构中，提供了覆盖基板的导体。电子器件覆盖导体的一部分，并且包括连接到导体的第一电极，第二电极和在第一和第二电极之间的绝缘层。导体的一部分被暴露以便进入其中。

35. 发明申请

US20080128691A1 Test structures for development of metal-insulator-metal (MIM) devices 有权
公开(公告)号：US20080128691A1
公开(公告)日：2008-06-05
申请号：US11633930
申请日：2006-12-05
申请人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
发明人： Steven Avanzino , Suzette K. Pangrle , Manuj Rathor , An Chen , Sameer Haddad , Nicholas Tripsas , Matthew Buynoski
IPC分类号： H01L23/58
CPC分类号： H01L22/32
摘要： In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

36. 发明申请

US20080112206A1 Method of selecting operating characteristics of a resistive memory device 有权
标题翻译：选择电阻式存储器件的工作特性的方法
公开(公告)号：US20080112206A1
公开(公告)日：2008-05-15
申请号：US11590378
申请日：2006-10-31
申请人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
发明人： Tzu-Ning Fang , Swaroop Kaza , An Chen , Sameer Haddad
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/52 , H01L27/2409 , H01L27/2436 , H01L45/10 , H01L45/1233 , H01L45/146 , H01L45/1633
摘要： In a method of providing an operating characteristic of a resistive memory device, material of an electrode thereof is selected to in turn provide a selected operating characteristic of the device. The material of the electrode may be reacted with material of an insulating layer of the resistive memory device to form a reaction layer, the selected operating characteristic being dependent on the presence of the reaction layer.
摘要翻译：在提供电阻存储器件的工作特性的方法中，选择其电极的材料，从而提供器件的选定工作特性。电极的材料可以与电阻式存储器件的绝缘层的材料反应以形成反应层，所选择的操作特性取决于反应层的存在。

37. 发明申请

US20060256608A1 Resistive memory device with improved data retention and reduced power 审中-公开
标题翻译：电阻式存储器件，具有改进的数据保持和降低功耗
公开(公告)号：US20060256608A1
公开(公告)日：2006-11-16
申请号：US11126800
申请日：2005-05-11
申请人： An Chen , Sameer Haddad , Tzu-Ning Fang
发明人： An Chen , Sameer Haddad , Tzu-Ning Fang
IPC分类号： G11C11/00
CPC分类号： G11C13/0009 , G11C13/0069 , G11C2013/009 , G11C2213/12 , G11C2213/15 , G11C2213/34 , G11C2213/56 , G11C2213/79
摘要： Provided herein is method of programming a resistive memory device, the resistive memory device including a first electrode, a second electrode, a passive layer between the first and second electrode, and an active layer between the first and second electrodes. In the programming method, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the active layer to the passive layer so that electronic charge carriers enter the active layer and are held by traps therein. In erasing the memory device, an electrical potential is applied across the first and second electrodes from higher to lower potential in the direction from the passive layer to the active layer so that electronic charge carriers are moved from the active layer.
摘要翻译：本文提供了对电阻式存储器件进行编程的方法，该电阻式存储器件包括第一电极，第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层。在编程方法中，在从有源层到无源层的方向上，跨越第一和第二电极施加电位从较高电位到较低的电位，使得电子载流子进入有源层并由其中的陷阱保持。在擦除存储器件时，在从无源层到有源层的方向上，跨越第一和第二电极的电势从较高电位施加到较低的电位，使得电子载流子从有源层移动。

38. 发明申请

US20060214304A1 Memory device with improved data retention 有权
标题翻译：具有改善数据保留性能的内存设备
公开(公告)号：US20060214304A1
公开(公告)日：2006-09-28
申请号：US11089708
申请日：2005-03-25
申请人： Zhida Lan , Sameer Haddad , Steven Avanzino
发明人： Zhida Lan , Sameer Haddad , Steven Avanzino
IPC分类号： H01L23/48
CPC分类号： G11C13/0009 , G11C2213/11 , G11C2213/15 , G11C2213/34 , G11C2213/56 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1641 , H01L2924/0002 , H01L2924/00
摘要： The present memory device include first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second and into which ions from the passive layer may be provided, and from which the ions may be provided into the passive layer. The active layer is made up of a base material and an impurity therein. The combined the material and impurity have a lower diffusion coefficient than the base material alone.
摘要翻译：本存储器件包括第一和第二电极，第一和第二电极之间的无源层，以及第一和第二电极之间的有源层，并且可以提供来自钝化层的离子，并且可以从其中提供离子被动层。有源层由基材和杂质构成。材料和杂质的组合具有比单独的基材更低的扩散系数。

39. 发明授权

US06953752B1 Reduced silicon gouging and common source line resistance in semiconductor devices 失效
标题翻译：在半导体器件中减少硅沟槽和普通源极线电阻
公开(公告)号：US06953752B1
公开(公告)日：2005-10-11
申请号：US10358756
申请日：2003-02-05
申请人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
发明人： Yue-Song He , Sameer Haddad , Zhi-Gang Wang , Richard Fastow
IPC分类号： H01L21/311 , H01L21/8247
CPC分类号： H01L27/11521
摘要： In the present method of undertaking a self aligned source etch of a semiconductor structure, a substrate has oxide thereon. First and second adjacent stacked gate structures are provided on the substrate. Oxide spacers are provided on the respective first and second adjacent sides of the first and second gate stacked structures, and polysilicon spacers are provided on the respective oxide spacers. A self aligned source etch is undertaken using the gate structures, oxide spacers, and polysilicon spacers as a mask. The polysilicon spacers are then removed, and metal, for example cobalt, is provided on the substrate, using the oxide spacers as a mask. A silicidation step is undertaken to form metal silicide common source line on the substrate.
摘要翻译：在进行半导体结构的自对准源蚀刻的本方法中，衬底在其上具有氧化物。第一和第二相邻的堆叠栅极结构设置在基板上。在第一和第二栅极堆叠结构的相应的第一和第二相邻侧上设置氧化物间隔物，并且在各个氧化物间隔物上设置多晶硅间隔物。使用栅极结构，氧化物间隔物和多晶硅间隔物作为掩模进行自对准源蚀刻。然后去除多晶硅间隔物，并且使用氧化物间隔物作为掩模在衬底上提供金属（例如钴）。进行硅化步骤以在衬底上形成金属硅化物共同源极线。

40. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

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