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31. 发明申请

US20090169214A1 UNIFIED OPTICAL CONNECTOR ARCHITECTURE 有权
标题翻译：统一的光学连接器架构
公开(公告)号：US20090169214A1
公开(公告)日：2009-07-02
申请号：US11965451
申请日：2007-12-27
申请人： Prashant R. Chandra
发明人： Prashant R. Chandra
IPC分类号： H04B10/00
CPC分类号： H04B10/801 , G06F13/4072 , H04J14/02 , H04J14/0257
摘要： A system, device, and method are disclosed. In one embodiment the system includes an optical link and a peripheral device optically coupled to the optical link. The system also includes a host controller, such as a graphics, network, or I/O controller. The system also includes a unified optical connector port, which is optically coupled to the optical link and electrically coupled to the first host controller. The port has a wavelength allocation unit that can allocate an optical wavelength for an optical signal that is utilized to communicate with the peripheral device. The port also includes an electrical-to-optical transmission unit capable of converting an electrical signal, received from the host controller, to the optical signal that was allocated at the first optical wavelength. The electrical-to-optical transmission unit is also capable of transmitting one or more data packets within the first optical signal to the peripheral device across the optical link.
摘要翻译：公开了一种系统，装置和方法。在一个实施例中，系统包括光链路和光耦合到光链路的外围设备。该系统还包括主机控制器，如图形，网络或I / O控制器。该系统还包括统一的光学连接器端口，其光学耦合到光学链路并电耦合到第一主机控制器。该端口具有波长分配单元，其可以分配用于与外围设备通信的光信号的光波长。该端口还包括能够将从主控制器接收的电信号转换为以第一光波长分配的光信号的电 - 光传输单元。电光传输单元还能够通过光链路将第一光信号内的一个或多个数据分组传送到外围设备。

32. 发明授权

US07213099B2 Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches 有权
标题翻译：利用非均匀分布的DRAM配置并检测范围内的存储器地址匹配的方法和装置
公开(公告)号：US07213099B2
公开(公告)日：2007-05-01
申请号：US10751263
申请日：2003-12-30
申请人： Chen-Chi Kuo , Sridhar Lakshmanamurthy , Rohit Natarajan , Kin-Yip Liu , Prashant R. Chandra , James D. Guilford
发明人： Chen-Chi Kuo , Sridhar Lakshmanamurthy , Rohit Natarajan , Kin-Yip Liu , Prashant R. Chandra , James D. Guilford
IPC分类号： G06F12/06
CPC分类号： G06F13/4243
摘要： Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.
摘要翻译：给出了在非均匀分布的DRAM配置中确定通道中的通道所有权和物理块位置的方法，软件和系统，以及检测范围内的存储器地址匹配。还可以在软件和/或硬件中实现的第一种方法在多个存储器通道之间非均匀地分配存储器，从存储器通道确定用于程序地址的所选择的存储器通道，并将程序地址映射到物理所选内存通道内的地址。也可以在软件和/或硬件中实现的第二种方法指定一系列存储器来执行地址匹配，监视存储器访问以及当以指定范围发生存储器访问时，执行特定功能。

33. 发明授权

US07210008B2 Memory controller for padding and stripping data in response to read and write commands 有权
标题翻译：内存控制器，用于根据读写命令填充和解除数据
公开(公告)号：US07210008B2
公开(公告)日：2007-04-24
申请号：US10741298
申请日：2003-12-18
申请人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： A memory controller that includes an interface to a first memory and an interface to a bus coupling the memory controller to at least one processor. The controller also includes circuitry, responsive to read and write commands received over the bus from the at least one processor, to shift data by an amount identified by at least some of the read and write commands.
摘要翻译：存储器控制器，其包括到第一存储器的接口以及将存储器控制器耦合到至少一个处理器的总线的接口。控制器还包括电路，响应于通过总线从至少一个处理器接收的读取和写入命令，将数据移位由至少一些读取和写入命令所标识的量。

34. 发明授权

US07185153B2 Packet assembly 失效
标题翻译：数据包组装
公开(公告)号：US07185153B2
公开(公告)日：2007-02-27
申请号：US10742189
申请日：2003-12-18
申请人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
发明人： Prashant R. Chandra , Sridhar Lakshmanamurthy , Chen-Chi Kuo , Rohit Natarajan , Mark Rosenbluth
IPC分类号： G06F12/00
CPC分类号： H04L69/166 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9052 , H04L67/02 , H04L69/16 , H04L69/329 , H04L2012/5652
摘要： In general, in one aspect, the disclosure describes a method of assembling a packet in memory. The method includes reading data included in a first segment of a packet divided into multiple segments and issuing a command to a memory controller that causes the memory controller to shift and write a subset of the read data to a memory coupled to the memory controller. The method also includes saving the remainder of the read data as a first residue, retrieving data included in a second segment of the packet, and writing at least a portion of the retrieved data and the first residue to the memory.
摘要翻译：一般来说，在一个方面，本公开描述了一种在存储器中组装分组的方法。该方法包括读取分组到多个分组的分组的第一分段中的数据，并向存储器控制器发出命令，该命令使得存储器控制器将读取的数据的子集移位并写入耦合到存储器控制器的存储器。该方法还包括将剩余的读取数据保存为第一残余，检索包含在分组的第二段中的数据，以及将所检索的数据和第一残差的至少一部分写入存储器。

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