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31. 发明授权

US06218892B1 Differential circuits employing forward body bias 失效
标题翻译：采用正向偏置的差分电路
公开(公告)号：US06218892B1
公开(公告)日：2001-04-17
申请号：US09256842
申请日：1999-02-24
申请人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
发明人： Krishnamurthy Soumyanath , Ali Keshavarzi , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0812 , H03L7/0995
摘要： In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.
摘要翻译：在一些实施例中，本发明包括具有差分放大器和体偏置控制电路的电路。差分放大器包括第一和第二FET晶体管的差分对，以响应于输入电压信号至少部分地控制输出电压信号，第一和第二FET晶体管被配置为匹配并具有主体。体偏置控制电路向身体提供体偏置电压信号，以将第一和第二FET晶体管置于正向体偏置状态。差分放大器和体偏置电路可用于读出放大器，比较器，压控振荡器，延迟锁定环路和锁相环路以及其他电路。

32. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

33. 发明授权

US07280425B2 Dual gate oxide one time programmable (OTP) antifuse cell 有权
标题翻译：双栅氧化层一次可编程（OTP）反熔丝
公开(公告)号：US07280425B2
公开(公告)日：2007-10-09
申请号：US11239903
申请日：2005-09-30
申请人： Ali Keshavarzi , Fabrice Paillet , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
发明人： Ali Keshavarzi , Fabrice Paillet , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/146 , G11C17/165 , G11C29/027
摘要： A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
摘要翻译：一次性可编程（OTP）单元包括耦合到反熔丝晶体管的存取晶体管。存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度，使得如果对反熔丝晶体管进行编程，则在存取晶体管的栅极/漏极结附近的电压不足以引起栅极氧化物存取晶体管分解。双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。

34. 发明授权

US07230846B2 Purge-based floating body memory 有权
标题翻译：基于清洗的浮体记忆
公开(公告)号：US07230846B2
公开(公告)日：2007-06-12
申请号：US11151982
申请日：2005-06-14
申请人： Ali Keshavarzi , Stephen H Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M Khellah , Yibin Ye , Vivek K De , Gerhard Schrom
发明人： Ali Keshavarzi , Stephen H Tang , Dinesh Somasekhar , Fabrice Paillet , Muhammad M Khellah , Yibin Ye , Vivek K De , Gerhard Schrom
IPC分类号： G11C11/34
CPC分类号： G11C11/404 , G11C2211/4016
摘要： In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
摘要翻译：通常，在一个方面，本公开描述了包括以行和列布置的多个存储单元的存储器阵列。每个存储单元包括具有能够存储电荷的浮动体的晶体管。多个字线和清除线与存储器单元的行互连。多个位线被连接到存储器单元的列。通过字线提供的驱动信号，清除线和位线可以协作以改变一个或多个存储器单元中的浮体区域的电荷。

35. 发明授权

US07102951B2 OTP antifuse cell and cell array 有权
标题翻译： OTP反熔丝电池和电池阵列
公开(公告)号：US07102951B2
公开(公告)日：2006-09-05
申请号：US10979605
申请日：2004-11-01
申请人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
发明人： Fabrice Paillet , Ali Keshavarzi , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Stephen H. Tang , Mohsen Alavi , Vivek K. De
IPC分类号： G11C17/18
CPC分类号： G11C17/146 , G11C17/16 , G11C17/18 , G11C29/027
摘要： Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.
摘要翻译：包括一次性可编程反熔丝电池的不同实施例。在一个实施例中，提供了包括反熔丝元件，高压器件和感测电路的电路。反熔丝元件在编程期间具有在感测/读取期间处于感测电压的电压提供端子和更高的编程电压。感测电路被配置为能够在编程期间对反熔丝元件进行编程，并且在感测期间感测反熔丝元件的状态。高电压设备耦合在反熔丝元件和感测电路之间，以在编程和感测期间将反熔断元件耦合到感测电路，并且在编程期间将感测电路与更高的编程电压保护性地屏蔽。

36. 发明授权

US06734498B2 Insulated channel field effect transistor with an electric field terminal region 有权
公开(公告)号：US06734498B2
公开(公告)日：2004-05-11
申请号：US09165483
申请日：1998-10-02
申请人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
发明人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
IPC分类号： H01L2701
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/78606 , H01L29/78645 , H01L29/78648
摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

37. 发明授权

US06632686B1 Silicon on insulator device design having improved floating body effect 失效
标题翻译：硅绝缘体器件设计具有改善的浮体效应
公开(公告)号：US06632686B1
公开(公告)日：2003-10-14
申请号：US09672696
申请日：2000-09-29
申请人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
发明人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
IPC分类号： H01L2166
CPC分类号： G06F17/5068 , G06F17/5063 , H01L27/1203
摘要： A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.
摘要翻译：提供了一种用于设计电子设备的方法。这可以包括确定电子设备的设计的电容比并改变设计以增加所述电子设备的电容比。电容比可以是C dj /（C dj + C sj + C BOX ），其中C dj 是漏 - 体结的电容C sj 是源体结的电容，C BOX 是掩埋氧化物层的电容。

38. 发明授权

US06459293B1 Multiple parameter testing with improved sensitivity 失效
标题翻译：灵敏度提高的多参数测试
公开(公告)号：US06459293B1
公开(公告)日：2002-10-01
申请号：US09672695
申请日：2000-09-29
申请人： Ali Keshavarzi , Kaushik K. Roy , Vivek K. De
发明人： Ali Keshavarzi , Kaushik K. Roy , Vivek K. De
IPC分类号： G01R3126
CPC分类号： G01R31/275
摘要： A method and device are provided for testing electronic devices on a chip. This may be accomplished by measuring current through a first electronic device and measuring a speed of the first electronic device. A determination may then be made whether the first electronic device is defective by comparing the measured current and the measured speed with a multi-parameter (i.e., IDDQ and FMAX) threshold level.
摘要翻译：提供了一种用于测试芯片上的电子设备的方法和装置。这可以通过测量通过第一电子设备的电流并测量第一电子设备的速度来实现。然后可以通过将测量的电流和测量的速度与多参数（即，IDDQ和FMAX）阈值水平进行比较来确定第一电子设备是否有缺陷。

39. 发明授权

US06218895B1 Multiple well transistor circuits having forward body bias 失效
标题翻译：具有前向偏置的多个阱晶体管电路
公开(公告)号：US06218895B1
公开(公告)日：2001-04-17
申请号：US09078424
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.
摘要翻译：在本发明的一个实施例中，半导体电路包括衬底和形成在衬底中的第一阱。在第一阱中形成第一组场效应晶体管，并且具有第一主体。该电路包括第一体电压，以使第一组场效应晶体管偏转第一体。电路包括第一隔离结构，以在第一阱中容纳第一体电压。在另一实施例中，电路还包括具有非正向主体偏置的第二组场效应晶体管，并且第一隔离结构防止第一体电压影响第二组场效应晶体管的主体的电压。在另一个实施例中，与第二阱相邻的第二隔离结构在保持第二组场效应晶体管的第二阱中包含第二体电压。

40. 发明授权

US06181608B2 Dual Vt SRAM cell with bitline leakage control 有权
标题翻译：双Vt SRAM单元，具有位线泄漏控制
公开(公告)号：US06181608B2
公开(公告)日：2001-01-30
申请号：US09261915
申请日：1999-03-03
申请人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
发明人： Ali Keshavarzi , Kevin Zhang , Yibin Ye , Vivek K. De
IPC分类号： G11C1134
CPC分类号： G11C11/412 , G11C11/418
摘要： In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines. In some embodiments, the wordline voltage control circuitry asserts the wordline signal for a selected wordline corresponding to a memory cell selected to be read and underdrives the wordline signals for the wordlines not corresponding to the selected memory cell.
摘要翻译：在一些实施例中，本发明包括包括位线和位线＃，字线和存储器单元的集成电路。每个对应于一个字线的存储单元分别包括分别耦合在第一和第二存储节点之间的第一和第二传输晶体管，位线和位线＃分别耦合到第一和第二通道的栅极晶体管。存储单元包括交叉耦合在第一和第二存储节点之间的第一和第二反相器，其中第一和第二传输晶体管每个具有比第一和第二反相器的晶体管更低的阈值电压。耦合到字线的字线电压控制电路有选择地控制字线上的字线信号。在一些实施例中，字线电压控制电路为对应于被选择要读取的存储器单元选择的字线断言字线信号，并驱动不对应于所选存储单元的字线的字线信号。

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