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31. 发明授权

US06381253B1 Data transmission system and method for interconnecting sending and receiving analog devices primarily through data channels 失效
标题翻译：主要通过数据通道互连发送和接收模拟设备的数据传输系统和方法
公开(公告)号：US06381253B1
公开(公告)日：2002-04-30
申请号：US09046489
申请日：1998-03-23
申请人： Alain Benayoun , Patrick Michel , Dominique Vinot , Jean-Francois Le Pennec
发明人： Alain Benayoun , Patrick Michel , Dominique Vinot , Jean-Francois Le Pennec
IPC分类号： H04L1216
CPC分类号： H04N1/00312 , H04L12/2854 , H04N1/00281 , H04N1/32005 , H04N2201/0015 , H04Q11/0471 , H04Q2213/13031 , H04Q2213/13034 , H04Q2213/1309 , H04Q2213/13106 , H04Q2213/13174 , H04Q2213/13176 , H04Q2213/13179 , H04Q2213/13199 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332
摘要： In a system and method of setting a data communication through an Integrated Service Digital Network (ISDN) between a transmitting analog device connected to a transmitting Terminal Adapter interfacing the ISDN network, a receiving analog device is connected to a receiving Terminal Adapter interfacing the ISDN network in a data communication system wherein a plurality of transmitting analog devices are connected and transmit data to a plurality of receiving analog devices primarily through a data channel and without device identification therein.
摘要翻译：在与连接到ISDN网络的发送终端适配器连接的发送模拟设备之间通过综合业务数字网（ISDN）设置数据通信的系统和方法中，接收模拟设备连接到接入ISDN网络的接收终端适配器在数据通信系统中，其中多个发送模拟设备被连接，并且主要通过数据信道向多个接收模拟设备发送数据，并且其中没有设备标识。

32. 发明授权

US06341346B1 Method for comparison between a pattern sequence and a variable length key 有权
标题翻译：模式序列与可变长度密钥之间进行比较的方法
公开(公告)号：US06341346B1
公开(公告)日：2002-01-22
申请号：US09245182
申请日：1999-02-05
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F9305
CPC分类号： G06F9/30018 , G06F9/30021
摘要： A method is disclosed for comparing a pattern sequence with a variable length key. A first bit of this sequence is identified by a pointer, the length and the location of the key are identified by a code word (W, S), the method includes a preliminary step of identifying the sequence and then performing a comparison with the variable length key.
摘要翻译：公开了一种用于将模式序列与可变长度密钥进行比较的方法。该序列的第一位由指针识别，密钥的长度和位置由码字（W，S）标识，该方法包括识别序列，然后与变量进行比较的初步步骤长度键。

33. 发明授权

US5828891A Multilevel interrupt device 失效
标题翻译：多级中断装置
公开(公告)号：US5828891A
公开(公告)日：1998-10-27
申请号：US766689
申请日：1996-12-13
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel
IPC分类号： G06F13/24 , G06F9/48 , G06F13/26 , G06F9/46
CPC分类号： G06F13/26
摘要： The invention relates to multilevel interrupt device (10) using a common microprocessor interrupt signal (101) to process interrupt signals (INT1, . . . , INTN) received from N peripheral chips. This device (10) is connected to a microprocessor (100) and N peripheral chips (200,210,230) through data/address busses (108,110) and it is also connected to a memory (150) by an additional bus (112). An interrupt operation starts when any one of the peripheral chips activates an interrupt signal through OR gate (220) detected by the microprocessor. The invention avoids to involve the microprocessor in the determination of the interrupt requester except for the generation of a common start.sub.-- address decoded by logic (180) for starting interrupt operations and a common end.sub.-- address decoded by logic (190) for ending it. Owing to the start.sub.-- address and the interrupt signals (173,174) received, latch (170) generates a translated address to memory (150) through a multiplexer (160) to start the corresponding interrupt routine stored at this translated address. The activation of any one of the peripheral chips leads to the reading of the corresponding interrupt routine stored in the memory without requiring any action of the microprocessor. The number of interrupt routines depends on the possible combinations of the N interrupt signals.
摘要翻译：本发明涉及使用公共微处理器中断信号（101）来处理从N个外围芯片接收的中断信号（INT1，...，INTN）的多电平中断装置（10）。该设备（10）通过数据/地址总线（108,110）连接到微处理器（100）和N个外围芯片（200,210,230），并且还通过附加总线（112）连接到存储器（150）。当任何一个外围芯片通过由微处理器检测到的或门（220）激活中断信号时，中断操作开始。本发明避免涉及微处理器确定中断请求者，除了生成由用于启动中断操作的逻辑（180）解码的公共起始地址以及由逻辑（190）解码以用于结束它的公共结束地址。由于接收到起始地址和中断信号（173,174），锁存器（170）通过多路复用器（160）产生到存储器（150）的转换地址，以启动存储在该翻译地址处的相应中断程序。任何一个外围芯片的激活导致读取存储在存储器中的相应的中断程序，而不需要微处理器的任何动作。中断程序的数量取决于N个中断信号的可能组合。

34. 发明授权

US5771262A Impedance adapter for network coupler cable 失效
标题翻译：网络耦合器电缆阻抗适配器
公开(公告)号：US5771262A
公开(公告)日：1998-06-23
申请号：US716077
申请日：1996-09-19
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Henri Giuliano
IPC分类号： H04L25/02 , H03H11/28 , H04B3/02 , H04B3/00
CPC分类号： H04B3/02 , H03H11/28
摘要： The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109). This circuit (109) determines if the resistors value selected by the magnetic coils of said impedance switching circuit (110) is equal or not equal to the impedance of the network lines (106,105). Thus, it compares VS to a voltage Vref (25) to generate an output which selects and activates the correct magnetic coil for changing or keeping equal the resistors of the receive/transmit impedance network (102,103) currently connected to the network lines (105,106).
摘要翻译：本发明提供一种阻抗适配器，其通过与所连接的发射机/接收机（100,101）串联/并行安装的各种阻抗的受控切换，自动切换到与网络发射/接收线路阻抗（105,106）匹配的阻抗。对于高速适配器，由于高传输速率，需要一个平衡的发射器/接收器来限制串扰效应。发射/接收阻抗适配网络（102-103）由电阻器和继电器触点的串联/并联网络组成，其由阻抗开关电路（110）的磁线圈独立地切换，并且具有与不同的不同网络阻抗匹配的值国家规定。通过使用双偏压电压技术的原理，测量电路（108）检测向上和向下的电压（VA，VB），VB放大2以产生模拟信号VS（VS = VA-2VB）到控制逻辑电路 109）。该电路（109）确定由所述阻抗开关电路（110）的磁线圈选择的电阻值是否等于网线（106,105）的阻抗。因此，它将VS与电压Vref（25）进行比较以产生输出，该输出选择并激活正确的磁线圈，用于改变或保持与当前连接到网络线路（105,106）的接收/发射阻抗网络（102,103）的电阻相等，。

35. 发明申请

US20110072353A1 TIME-BASED GRAPHIC NETWORK REPORTING NAVIGATOR 有权
标题翻译：基于时间的图形网络报告导航仪
公开(公告)号：US20110072353A1
公开(公告)日：2011-03-24
申请号：US12613707
申请日：2009-11-06
申请人： Jean-Francois Le Pennec , Jacques Fieschi , Marc Gatignol
发明人： Jean-Francois Le Pennec , Jacques Fieschi , Marc Gatignol
IPC分类号： G06F15/177
CPC分类号： H04L41/0622 , H04L41/064 , H04L43/045 , H04L43/067
摘要： The presently disclosed embodiments are directed to representing network performance information using a network map by partitioning a graphical affordance representing a network element in the network map into segmented sections in accordance with a temporal encoding scheme to encode temporal information in the network map. The segmented sections are encoded using a performance encoding scheme to identify a level of performance associated with the segmented sections so that the network map depicts a performance of the network element over time.
摘要翻译：目前公开的实施例涉及通过使用网络映射来表示网络性能信息，所述网络映射通过根据时间编码方案将网络图中的网络元素的图形能力划分为分段部分，以对网络图中的时间信息进行编码。分段部分使用性能编码方案进行编码，以识别与分段部分相关联的性能级别，使得网络图描绘网络元素随时间的性能。

36. 发明授权

US06628198B2 Security system for preventing a personal computer from being stolen or used by unauthorized people 失效
标题翻译：防止个人电脑被未经授权的人盗用或使用的安全系统
公开(公告)号：US06628198B2
公开(公告)日：2003-09-30
申请号：US09683776
申请日：2002-02-13
申请人： Jacques Fieschi , Jean-Francois Le Pennec
发明人： Jacques Fieschi , Jean-Francois Le Pennec
IPC分类号： G08B1314
CPC分类号： G06F21/88
摘要： Security system for preventing a personal computer (PC) including at least a location in the PC adapted to receive a PCMCIA card from being used by unauthorized people including an extractable card having a connection adapted to insert the extractable card into the location for receiving a PCMCIA card. Further included are a processor and a wireless transceiver for remotely transmitting alarm information relative to the PC. Still further included is a program stored in the memory of the PC for communicating with the processor in order to activate selected security functions.
摘要翻译：用于防止个人计算机（PC）的安全系统包括至少适于接收PCMCIA卡的位置的个人计算机（PC），以被未经授权的人使用，包括具有适于将可提取卡插入到用于接收PCMCIA的位置的连接的可提取卡卡。还包括处理器和无线收发器，用于相对于PC远程传输报警信息。还包括存储在PC的存储器中用于与处理器进行通信以便激活所选择的安全功能的程序。

37. 发明授权

US07383311B2 Hardware device for processing the tasks of an algorithm in parallel 失效
标题翻译：用于并行处理算法任务的硬件设备
公开(公告)号：US07383311B2
公开(公告)日：2008-06-03
申请号：US11322378
申请日：2006-01-03
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Claude Pin
IPC分类号： G06F15/16 , G06F9/46
CPC分类号： G06F9/30101 , G06F9/3836
摘要： A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being either one process or one decision or one process together with a following decision. A task interconnection logic block (16) is connected to each task unit for communicating actions from a source task unit to a destination task unit. Each task unit includes a processor (18) for processing the steps of the associated task when a received action requests such a processing. A status manager (20) handles actions coming from other task units and builds actions to be sent to other task units
摘要翻译：一种硬件设备，用于处理具有多个进程数量的处理类型的算法的任务取决于二进制决定的任务具有多个任务单元（10,12,14），每个任务单元与任务相关联定义为一个过程或一个决策或一个过程以及以下决定。任务互连逻辑块（16）连接到每个任务单元，用于将来自源任务单元的操作传送到目的地任务单元。每个任务单元包括处理器（18），用于在接收的动作请求这样的处理时处理相关任务的步骤。状态管理器（20）处理来自其他任务单元的动作，并构建要发送到其他任务单元的动作

38. 发明授权

US06996111B1 ATM node having local error correcting procedures 失效
标题翻译： ATM节点具有本地纠错程序
公开(公告)号：US06996111B1
公开(公告)日：2006-02-07
申请号：US09991000
申请日：2001-11-14
申请人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
发明人： Alain Benayoun , Jean-Francois Le Pennec , Patrick Michel , Gilles Toubol
IPC分类号： H04L12/56
CPC分类号： H04Q11/0478 , H04L2012/5647 , H04L2012/5652
摘要： A node for a telecommunications network has a segmentation and reassembly module (SAR module) to perform segmentation and reassembly (SAR) on cells received by the node, the SAR module particularly providing Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation (referred to as VCI/VPI translation), and has a direct memory access (DMA) mechanism for a storage external to the SAR module, the SAR module performing a first DMA access when the VCI/VPI translation are representative of an error code correcting (ECC) procedure to be carried out in the node, and the SAR module performing a second DMA access when the VCI/VPI translation corresponds to a message that does not require a local ECC procedure. A coder/decoder module performs an ECC procedure on the cells. A controller controls the coder/decoder module to perform an error correcting procedure in response to the detection of the first DMA access. The first DMA access uses a first address and the second DMA uses a second address. A Reed-Solomon coder-decoder or a Hamming coder-decoder may be used to perform the ECC procedure. An address decoder interprets the VCI/VPI identifiers to control whether or not an ECC procedure is done.
摘要翻译：用于电信网络的节点具有分段和重组模块（SAR模块），用于对由节点接收的小区执行分段和重组（SAR），SAR模块特别提供虚拟信道标识符（VCI）和虚拟路径标识符（VPI）转换（称为VCI / VPI转换），并且具有用于SAR模块外部的存储器的直接存储器访问（DMA）机制，当VCI / VPI转换代表纠错码时，SAR模块执行第一DMA访问（ECC）过程，并且当VCI / VPI转换对应于不需要本地ECC过程的消息时，SAR模块执行第二DMA访问。编码器/解码器模块对单元执行ECC过程。控制器控制编码器/解码器模块响应于第一DMA访问的检测来执行纠错过程。第一个DMA访问使用第一个地址，第二个DMA使用第二个地址。可以使用里德 - 所罗门编码器解码器或汉明编码器解码器来执行ECC过程。地址解码器解释VCI / VPI标识符以控制ECC过程是否完成。

39. 发明授权

US06968386B1 System for transferring data files between a user workstation and web server 失效
标题翻译：用于在用户工作站和Web服务器之间传输数据文件的系统
公开(公告)号：US06968386B1
公开(公告)日：2005-11-22
申请号：US09660043
申请日：2000-09-12
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Claude Pin
IPC分类号： G06F13/12 , G06F15/167 , G06F15/16 , H04B1/38 , H04L5/16
CPC分类号： G06F13/128
摘要： System for transferring a data file from a web server to a user workstation through a network and reciprocally, the user workstation including a hard disk (205) for storing the data file being transferred over a SCSI bus (208). The user workstation includes a dual-port memory (304) for storing temporarily the data file, a network logic unit (302) interconnected between the network and the input port of the dual-port memory for receiving the data file from the network and transmitting it to the dual-port memory, and a SCSI logic unit (303) interconnected between the output port of the dual-port memory and the SCSI bus for transferring the data file from the dual-port memory to the hard disk over the SCSI bus and reciprocally.
摘要翻译：用于通过网络将数据文件从网络服务器传送到用户工作站的系统，所述用户工作站包括用于存储通过SCSI总线（208）传送的数据文件的硬盘（205）。用户工作站包括用于临时存储数据文件的双端口存储器（304），在网络与双端口存储器的输入端口之间互连的网络逻辑单元（302），用于从网络接收数据文件并发送双端口存储器和在双端口存储器的输出端口和SCSI总线之间互连的SCSI逻辑单元（303），用于通过SCSI总线将数据文件从双端口存储器传送到硬盘并相互地。

40. 发明授权

US06804257B1 System and method for framing and protecting variable-lenght packet streams 有权
标题翻译：用于构建和保护可变长度数据包流的系统和方法
公开(公告)号：US06804257B1
公开(公告)日：2004-10-12
申请号：US09664931
申请日：2000-09-19
申请人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
发明人： Alain Benayoun , Patrick Michel , Jean-Francois Le Pennec , Gilles Toubol
IPC分类号： H04J324
CPC分类号： H04L1/0061 , H04L1/0041 , H04L1/0072 , H04L1/008 , H04L1/0083 , H04L1/0085 , H04L7/048 , H04L7/10
摘要： A method and a system for framing variable-length packets in a data communications system are disclosed. The successive variable-length packets carrying users' data, are formed in a stream of chained packets comprising a header. Two CRC's are computed. One over the data and another one over the header however, including also the data CRC of the immediate previous packet, thus chaining successive packets in a steam of such packets. The invention also assumes that encryption is performed independently over header and corresponding CRC's and, on the other hand, over the data of current packet. The invention allows to better adapt the transportation of multi-media users' data in packets of variable-lengths while securing transport by chaining successive packets, thus preventing that accidental or malicious deletion and insertion of packets occur and remain undetected. Also, the invention permits that intermediate transport nodes, owning keys to decrypt headers, may perform packet add/drop multiplexing without requiring that users' data need to be decrypted on their way to their final destination.
摘要翻译：公开了一种用于在数据通信系统中成帧可变长度分组的方法和系统。携带用户数据的连续可变长度分组形成在包括报头的链式分组流中。计算两个CRC。然而，一个在数据上，另一个在报头上，还包括紧接在前的分组的数据CRC，从而链接这些分组的蒸汽中的连续分组。本发明还假定加密是在头部和对应的CRC上独立执行的，另一方面超过当前分组的数据。本发明允许通过链接连续分组来更好地适应多媒体用户数据在可变长度的分组中的传输，同时通过链接连续分组来保护传输，从而防止分组的意外或恶意删除和插入发生并且不被检测。此外，本发明允许拥有密钥来解密报头的中间传输节点可以执行分组添加/丢弃复用，而不需要在到达其最终目的地的途中对用户的数据进行解密。

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