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31. 发明申请

US20060129318A1 Symbol position detection device and symbol position detection method 审中-公开
标题翻译：符号位置检测装置和符号位置检测方法
公开(公告)号：US20060129318A1
公开(公告)日：2006-06-15
申请号：US10540022
申请日：2003-12-26
申请人： Yuji Mizuguchi , Nobuhiko Yasui , Noboru Katta , Takahisa Sakai , Yutaka Takahira , Hirotsugu Kawada , Toshitomo Umei , Takashi Akita , Takefumi Yoshikawa , Shiro Dosho
发明人： Yuji Mizuguchi , Nobuhiko Yasui , Noboru Katta , Takahisa Sakai , Yutaka Takahira , Hirotsugu Kawada , Toshitomo Umei , Takashi Akita , Takefumi Yoshikawa , Shiro Dosho
IPC分类号： G06F19/00
CPC分类号： H04L7/0334 , H04L7/005 , H04L7/027 , H04L7/033
摘要： To a data reception device, a signal having a frequency of 12.5 MHz and including data is transmitted. The data reception device generates a clock B having a frequency of 400 MHz of (1) in FIG. 8, and performs sampling for the above-described 12.5 MHz signal based on the clock B ((2) in FIG. 8). Then, the data reception device detects zero cross points of the sampled data, and generates a 25 MHz frequency clock signal indicating the zero cross points ((3) in FIG. 8). Next, the data reception device generates, by delaying the generated clock signal by the time amount corresponding to eight clocks ((4) in FIG. 8), a 25 MHz signal indicating symbol points. Thus, symbol points can be detected.
摘要翻译：向数据接收装置发送频率为12.5MHz并包括数据的信号。数据接收装置在图1中生成具有400MHz的频率的时钟B（1）。基于时钟B（图8的（2））对上述12.5MHz信号进行采样。然后，数据接收装置检测取样数据的零交叉点，生成表示零交叉点（图8的（3））的25MHz频率时钟信号。接下来，数据接收装置通过将生成的时钟信号延迟与8个时钟（图8的（4））对应的时间量来生成表示符号点的25MHz信号。因此，可以检测符号点。

32. 发明申请

US20050135505A1 Frequency modulation circuit 有权
标题翻译：频率调制电路
公开(公告)号：US20050135505A1
公开(公告)日：2005-06-23
申请号：US11000224
申请日：2004-12-01
申请人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
发明人： Tsuyoshi Ebuchi , Takefumi Yoshikawa , Yukio Arima
IPC分类号： H03C3/00 , H03K7/06 , H03L7/093 , H04B15/02 , H04B3/46
CPC分类号： H04B15/02 , H03K7/06 , H04B2215/067
摘要： The frequency modulation circuit includes: a phase shift section for receiving a multiphase clock signal composed of a plurality of clock signals having a predetermined phase difference therebetween and shifting the phase of the multiphase clock signal; a clock selection section for selecting a clock signal constituting the multiphase clock signal output from the phase shift section; and a modulation control section for controlling the phase shift section and the clock selection section so that a clock signal having a frequency different from the frequency of the multiphase clock signal input into the phase shift section is output from the clock selection section.
摘要翻译：频率调制电路包括：相移部，用于接收由多个时钟信号组成的多相时钟信号，所述多个时钟信号具有预定的相位差，并移位多相时钟信号的相位; 时钟选择部分，用于选择构成从相移部分输出的多相时钟信号的时钟信号; 以及调制控制部分，用于控制相移部分和时钟选择部分，使得从时钟选择部分输出具有与输入到相移部分的多相时钟信号的频率不同的频率的时钟信号。

33. 发明授权

US06735710B1 Clock extraction device 失效
标题翻译：时钟提取装置，用于分别具有公共锁相环来提取对应于多个输入端口的不同时钟
公开(公告)号：US06735710B1
公开(公告)日：2004-05-11
申请号：US09655717
申请日：2000-09-05
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： G06F104
CPC分类号： H04L7/0337 , H03L7/0995 , H04L7/042
摘要： Incoming serial data is quantized by 3-times oversampling to obtain a first datastream. By the EXOR of adjacent bits in the datastream, a second datastream which specifies transient points in the first datastream is produced from the first datastream. Reference is made to the third bit from each transient point in the second datastream and to bits positioned on each side of the third bit. If there exists no transient point in any one of these two bits, then the third bit is a boundary. On the other hand, if there exists a transient point in either of the two bits, the bit where the transient point exists is a boundary. In this way, a third datastream is produced. Then, the time-series EXOR of the third datastream and a clock bitstream is performed to produce a final clock bitstream.
摘要翻译：通过3次过采样对进入的串行数据进行量化以获得第一数据流。通过数据流中相邻位的EXOR，从第一数据流产生指定第一数据流中的瞬时点的第二数据流。参考第二个数据流中每个瞬态点的第三位和位于第三位的每一侧的位。如果在这两个位中的任何一个中不存在瞬态点，则第三位是边界。另一方面，如果在两个位中的任一位存在瞬态点，则存在瞬态点的位是边界。以这种方式，产生第三数据流。然后，执行第三数据流的时间序列EXOR和时钟比特流以产生最终的时钟比特流。

34. 发明授权

US06690217B2 Data width corrector 有权
标题翻译：数据宽度校正器
公开(公告)号：US06690217B2
公开(公告)日：2004-02-10
申请号：US10139327
申请日：2002-05-07
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： H03K3017
CPC分类号： H03K5/1565 , H04L25/08
摘要： The data width corrector of the invention adjusts the data width appropriately even for data in which cross points have already deviated at the time of input. A data adjusting buffer changes a differential signal received from outside to single-phase receive data and outputs the receive data. A charge pump compares the average time of the HIGH period between the receive data and latch data latched with a latch clock having the same frequency, and supplies the results to the data adjusting buffer. The data adjusting buffer adjusts the duty of the receive data according to the received comparison results.
摘要翻译：本发明的数据宽度校正器即使在输入时交叉点已经偏离的数据也适当地调整数据宽度。数据调整缓冲器将从外部接收到的差分信号改变为单相接收数据，并输出接收数据。电荷泵将接收数据和锁存的锁存数据之间的HIGH周期的平均时间与具有相同频率的锁存时钟进行比较，并将结果提供给数据调整缓冲器。数据调整缓冲器根据接收到的比较结果调整接收数据的占空比。

35. 发明授权

US06686779B2 Driver circuit for differentially outputting data from internal circuitry of an LSI to outside the LSI 失效
标题翻译：用于从LSI的内部电路将数据差分输出到LSI外部的驱动电路
公开(公告)号：US06686779B2
公开(公告)日：2004-02-03
申请号：US10227758
申请日：2002-08-27
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： H03K300
CPC分类号： H04L25/028 , H03K19/00323 , H04L25/0272 , H04L25/0282
摘要： The driver circuit includes a constant current section, a first pad, a second pad, a first switching element, a second switching element, a first resistor, a second resistor, and a control section. The constant current section outputs a prescribed positive or negative current. The first switching element is connected between an output node of the constant current section and the first pad and turned ON/OFF in response to a first signal. The second switching element is connected between the output node of the constant current section and the second pad and turned ON/OFF in response to a second signal. The second signal is complementary to the first signal. The first resistor is connected between a first node receiving a first voltage and the first pad. The second resistor is connected between the first node and the second node. The control section controls a potential at the output node of the constant current section to a prescribed potential.
摘要翻译：驱动电路包括恒流部分，第一焊盘，第二焊盘，第一开关元件，第二开关元件，第一电阻器，第二电阻器和控制部件。恒定电流部分输出规定的正或负电流。第一开关元件连接在恒定电流部分的输出节点和第一焊盘之间，并响应于第一信号而导通/截止。第二开关元件连接在恒定电流部分的输出节点和第二焊盘之间，并响应于第二信号而导通/截止。第二信号与第一信号互补。第一电阻器连接在接收第一电压的第一节点和第一电池块之间。第二电阻器连接在第一节点和第二节点之间。控制部将恒定电流部的输出节点的电位控制为规定电位。

36. 发明授权

US06542552B1 Data transmitter 失效
标题翻译：数据发送器
公开(公告)号：US06542552B1
公开(公告)日：2003-04-01
申请号：US09468830
申请日：1999-12-22
申请人： Takefumi Yoshikawa , Yutaka Terada
发明人： Takefumi Yoshikawa , Yutaka Terada
IPC分类号： H03B300
CPC分类号： G06F1/10 , H04L7/0008 , H04L7/0037 , H04L7/0091 , H04L7/04
摘要： A data transmitter according to the present invention includes driver, transmission line and receiver. The receiver includes a transition pulse generator for generating a transition pulse simultaneously with the transition of a data signal output from the driver. If an edge of an internal clock signal overlaps with the transition pulse being applied, then the receiver does not latch the data signal in synchronism with the edge of the internal clock signal. Instead, the receiver obtains and retains a data value opposite to the previous cycle one. On the other hand, while no transition pulses are being applied, the receiver latches the data signal normally responsive to the internal clock signal. Accordingly, the receiver can always accurately retain the very data transmitted through the transmission line, thus improving the reliability of the data received and realizing high-speed data transmission even if the internal clock signal has lagged with respect to the data signal.
摘要翻译：根据本发明的数据发送器包括驱动器，传输线和接收器。接收机包括转换脉冲发生器，用于与从驾驶员输出的数据信号的转变同时产生转换脉冲。如果内部时钟信号的边沿与施加的转换脉冲重叠，则接收器不会与内部时钟信号的边沿同步地锁存数据信号。相反，接收器获得并保留与前一个周期相反的数据值。另一方面，当没有施加转换脉冲时，接收器通常响应于内部时钟信号来锁存数据信号。因此，即使内部时钟信号相对于数据信号滞后，接收机总是可以准确地保持通过传输线传输的非常数据，从而提高接收的数据的可靠性并实现高速数据传输。

37. 发明授权

US06323756B1 Data transmitter 有权
标题翻译：数据发送器
公开(公告)号：US06323756B1
公开(公告)日：2001-11-27
申请号：US09486868
申请日：2000-05-26
申请人： Takefumi Yoshikawa , Toru Iwata , Hiroyuki Yamauchi
发明人： Takefumi Yoshikawa , Toru Iwata , Hiroyuki Yamauchi
IPC分类号： H04M1104
CPC分类号： H03K19/017545 , H03K19/0013
摘要： The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.
摘要翻译：本发明的数据传输装置1a包括用于发送数据的驱动器10，用于接收从驱动器10发送的数据的接收器20，用于连接驱动器10和接收器20的传输线路径30和可变阻抗元件40具有可控制的可变阻抗。可变阻抗元件40连接到传输线路径30.数据传输线设备1a可以降低功耗并产生偏斜。

38. 发明授权

US06199150B1 Data memory apparatus forming memory map having areas with different access speeds 失效
标题翻译：数据存储装置形成具有不同访问速度区域的存储器映射
公开(公告)号：US06199150B1
公开(公告)日：2001-03-06
申请号：US09114429
申请日：1998-07-13
申请人： Takefumi Yoshikawa
发明人： Takefumi Yoshikawa
IPC分类号： G06F1206
CPC分类号： G06F12/08
摘要： A data memory apparatus includes at least one memory device forming a memory map including at least a first memory area and a second memory area; and an access control unit for controlling access to the at least one memory device so that an access speed to the first memory area is different from an access speed to the second memory area.
摘要翻译：数据存储装置包括形成至少包括第一存储区和第二存储区的存储器映射的至少一个存储器装置; 以及访问控制单元，用于控制对至少一个存储设备的访问，使得到第一存储区域的访问速度不同于到第二存储区域的访问速度。

39. 发明授权

US5575851A Die coater 失效
标题翻译：模具涂布机
公开(公告)号：US5575851A
公开(公告)日：1996-11-19
申请号：US141638
申请日：1993-10-27
申请人： Tetsuo Abe , Hitoshi Hatashima , Kunihiko Ichikawa , Takefumi Yoshikawa
发明人： Tetsuo Abe , Hitoshi Hatashima , Kunihiko Ichikawa , Takefumi Yoshikawa
IPC分类号： B05C5/02 , B29C47/16 , B05C3/18
CPC分类号： B29C47/16 , B05C5/0266 , B29C47/0019 , B29C47/003 , B29C47/0033
摘要： Disclosed herein is a die coater comprising a die composed of upper and lower mold-pieces which form a manifold and a slit extending from the manifold, an inner deckle shaft disposed in the manifold, a deckle disposed in the slit in a fluid-tight state, and a deckle guide; the inner deckle shaft having a fluid-tight portion near an end thereof and capable of moving with its fluid-tight state kept, the deckle and the deckle guide being secured to the inner deckle shaft, and the deckle being connected with the fluid-tight portion of the inner deckle shaft.
摘要翻译：本文公开了一种模具涂布机，其包括由上模具和下模具构成的模具，所述模具形成歧管和从歧管延伸的狭缝，设置在歧管中的内层板轴，以流体密封状态设置在狭缝中的板，和一个甲板导轨; 内层板轴在其端部附近具有流体密封部分，并且能够保持其流体密封状态移动，甲板和甲板导向件固定到内板轴上，并且该盖板与流体密封连接内板轴的一部分。

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