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31. 发明授权

US07952950B2 Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit 有权
标题翻译：包括反熔丝电路的半导体器件，以及将地址写入反熔丝电路的方法
公开(公告)号：US07952950B2
公开(公告)日：2011-05-31
申请号：US12289196
申请日：2008-10-22
申请人： Shinichi Miyatake , Sumio Ogawa
发明人： Shinichi Miyatake , Sumio Ogawa
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2029/4402
摘要： An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
摘要翻译：根据本发明的反熔丝电路包括以非易失性方式保存数据的反熔丝元件和临时保持要写入反熔丝元件的数据的锁存电路。对锁存电路的写入可以以纳秒的量级执行，因此即使当各种不同的不同地址被写入多个芯片时，也可以在非常短的时间内完成对锁存电路的写入处理。由此，可以对于芯片并行地执行写入反熔丝元件的实际处理，结果，可以高速地执行写入反熔丝元件的处理。

32. 发明申请

US20100244908A1 Semiconductor device having a complementary field effect transistor 有权
标题翻译：具有互补场效应晶体管的半导体器件
公开(公告)号：US20100244908A1
公开(公告)日：2010-09-30
申请号：US12662044
申请日：2010-03-29
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： G05F3/16
CPC分类号： G05F1/463 , G05F1/462 , G05F3/205 , G05F3/242 , G11C5/147
摘要： A semiconductor device prevents the ON current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a buffer circuit that generates a power-supply voltage of a CMOS; a first replica transistor that is a replica of a p-channel MOS transistor forming the CMOS, and is diode-connected; a second replica transistor that is a replica of an n-channel MOS transistor forming the CMOS, and is diode-connected; and a voltage controller that controls the voltage between the anode and cathode of the replica transistors so that the current value of the current flowing into the replica transistor becomes equal to a given target value. In this semiconductor device, the buffer circuit generates the power-supply voltage, with the target voltage being a voltage that is controlled by the voltage controller.
摘要翻译：半导体器件防止互补场效应晶体管的导通电流随着环境温度的变化而变化。半导体器件包括：产生CMOS的电源电压的缓冲电路; 第一复制晶体管，其是形成CMOS的p沟道MOS晶体管的复制品，并且是二极管连接的; 第二复制晶体管，其是形成CMOS的n沟道MOS晶体管的复制品，并且是二极管连接的; 以及电压控制器，其控制复制晶体管的阳极和阴极之间的电压，使得流入复制晶体管的电流的电流值等于给定的目标值。在该半导体器件中，缓冲电路产生电源电压，目标电压是由电压控制器控制的电压。

33. 发明申请

US20090109790A1 Semiconductor device including anti-fuse circuit, and method of writing address to anti-fuse circuit 有权
标题翻译：包括反熔丝电路的半导体器件，以及将地址写入反熔丝电路的方法
公开(公告)号：US20090109790A1
公开(公告)日：2009-04-30
申请号：US12289196
申请日：2008-10-22
申请人： Shinichi Miyatake , Sumio Ogawa
发明人： Shinichi Miyatake , Sumio Ogawa
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C17/165 , G11C29/785 , G11C2029/4402
摘要： An anti-fuse circuit according to the present invention includes an anti-fuse element that holds data in a nonvolatile manner and a latch circuit that temporarily holds data to be written to the anti-fuse element. The writing to the latch circuit can be performed in the order of nanoseconds, and thus, even when the defective addresses respectively different are written in a plurality of chips, a writing process to the latch circuit can be completed in a very short period of time. Thereby, an actual process for writing to the anti-fuse element can be performed in parallel for the chips, and as a result, the process for writing to the anti-fuse element can be performed at high speed.
摘要翻译：根据本发明的反熔丝电路包括以非易失性方式保存数据的反熔丝元件和临时保持要写入反熔丝元件的数据的锁存电路。对锁存电路的写入可以以纳秒的量级执行，因此即使当各种不同的不同地址被写入多个芯片时，也可以在非常短的时间内完成对锁存电路的写入处理。由此，可以对于芯片并行地执行写入反熔丝元件的实际处理，结果，可以高速地执行写入反熔丝元件的处理。

34. 发明申请

US20090059702A1 Sense amplifier for semiconductor memory device 有权
标题翻译：用于半导体存储器件的检测放大器
公开(公告)号：US20090059702A1
公开(公告)日：2009-03-05
申请号：US12285527
申请日：2008-10-08
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

35. 发明授权

US07447091B2 Sense amplifier for semiconductor memory device 有权
标题翻译：用于半导体存储器件的检测放大器
公开(公告)号：US07447091B2
公开(公告)日：2008-11-04
申请号：US11706409
申请日：2007-02-15
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

36. 发明申请

US20080211058A1 Semiconductor device and method of manufacturing same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080211058A1
公开(公告)日：2008-09-04
申请号：US12007844
申请日：2008-01-16
申请人： Shintaro Asano , Kazutoshi Fukahori , Shinichi Miyatake
发明人： Shintaro Asano , Kazutoshi Fukahori , Shinichi Miyatake
IPC分类号： H01L21/441 , H01L29/86
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises one or more elements subjected to trimming, formed on a main surface side of a silicon substrate and that is/are to be laser trimmed, and an electrode lead of the element subjected to trimming disposed below the position of the element subjected to trimming. The electrode lead subjected to trimming comprises a diffusion layer formed in an uppermost layer of the silicon substrate. The diffusion layer is covered with a protection film made of doped polysilicon and is directly formed on the silicon substrate.
摘要翻译：半导体器件包括经过修整的一个或多个元件，形成在硅衬底的主表面侧并且被激光修整，并且经受修整的元件的电极引线设置在被施加的元件的位置下方修剪经过修整的电极引线包括形成在硅衬底的最上层中的扩散层。扩散层被由掺杂多晶硅制成的保护膜覆盖并直接形成在硅衬底上。

37. 发明授权

US07200061B2 Sense amplifier for semiconductor memory device 有权
公开(公告)号：US07200061B2
公开(公告)日：2007-04-03
申请号：US10534049
申请日：2002-11-08
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.

38. 发明授权

US06282141B1 Semiconductor memory device and memory system 有权
标题翻译：半导体存储器件和存储器系统
公开(公告)号：US06282141B1
公开(公告)日：2001-08-28
申请号：US09571512
申请日：2000-05-15
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C800
CPC分类号： G11C7/1069 , G11C7/1006 , G11C7/1051 , G11C11/406 , G11C11/40626 , G11C11/4096
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.
摘要翻译：根据特定写入操作模式的指定，同时选择不同存储器阵列中的两个存储器单元，以将写入信号的逻辑1与每个电容器中存在电荷的状态相关联。此外，写入信号的逻辑0与在电容器中不存在电荷以写入相同写入信号的状态相关联。根据特定读取操作模式的指定，同时选择不同存储器阵列中的两个动态存储单元，以将每个动态存储单元的电容器中存在电荷的状态与读取信号的逻辑1和关联响应于写入操作，具有读取信号的逻辑0的电容器中不存在电荷的状态。因此，优先输出两个读取信号的逻辑1。

39. 发明授权

US6064605A Semiconductor memory device and memory system 有权
公开(公告)号：US6064605A
公开(公告)日：2000-05-16
申请号：US395158
申请日：1999-09-14
申请人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
发明人： Masaya Muranaka , Shinichi Miyatake , Yukihide Suzuki , Kanehide Kenmizaki , Makoto Morino , Tetsuya Kitame
IPC分类号： G11C11/403 , G11C7/04 , G11C7/10 , G11C11/406 , G11C11/4096 , H01L27/10 , G11C7/00
CPC分类号： G11C7/1069 , G11C11/406 , G11C11/40626 , G11C11/4096 , G11C7/1006 , G11C7/1051
摘要： Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Further, a logic 0 of the write signal is associated with a state in which no electric charge exists in the capacitor to write the same write signal. Two dynamic memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific read operation mode to associate a state in which an electric charge exists in a capacitor of each dynamic memory cell with a logic 1 of a read signal and associate a state in which no electric charge exists in the capacitor with a logic 0 of the read signal in response to a write operation. Thus, the logics 1 of the two read signals are preferentially output.

40. 发明授权

US08222952B2 Semiconductor device having a complementary field effect transistor 失效
标题翻译：具有互补场效应晶体管的半导体器件
公开(公告)号：US08222952B2
公开(公告)日：2012-07-17
申请号：US12662038
申请日：2010-03-29
申请人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
发明人： Shinichi Miyatake , Seiji Narui , Hitoshi Tanaka
IPC分类号： H03K3/01
CPC分类号： H03K19/00361 , H03K19/0008 , H03K2217/0018
摘要： A semiconductor device prevents the OFF current of a complementary field effect transistor from varying with changes in ambient temperature. The semiconductor device includes: a substrate voltage generating circuit that generates the substrate voltage of an n-channel MOS transistor forming a CMOS; a replica transistor that is a replica of the n-channel MOS transistor, and is diode-connected; and a voltage applier that applies a voltage of a predetermined voltage value between the anode and cathode of the replica transistor. In this semiconductor device, the substrate voltage of the replica transistor is the substrate voltage generated by the substrate voltage generating circuit. The substrate voltage generating circuit controls the substrate voltage to be generated so that the current value of the current flowing into the replica transistor becomes equal to a given target value.
摘要翻译：半导体器件防止互补场效应晶体管的截止电流随着环境温度的变化而变化。半导体器件包括：衬底电压产生电路，其产生形成CMOS的n沟道MOS晶体管的衬底电压; 复制晶体管，其是n沟道MOS晶体管的复制品，并且是二极管连接的; 以及在复制晶体管的阳极和阴极之间施加预定电压值的电压的施加电压器。在该半导体器件中，复制晶体管的衬底电压是由衬底电压产生电路产生的衬底电压。衬底电压产生电路控制要产生的衬底电压，使得流入复制晶体管的电流的电流值等于给定的目标值。

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