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31. 发明申请

US20080128689A1 FLAT PANEL DISPLAYS COMPRISING A THIN-FILM TRANSISTOR HAVING A SEMICONDUCTIVE OXIDE IN ITS CHANNEL AND METHODS OF FABRICATING THE SAME FOR USE IN FLAT PANEL DISPLAYS 有权
标题翻译：平面板显示器，其包括在其通道中具有半导体氧化物的薄膜晶体管及其制造方法用于平板显示器
公开(公告)号：US20080128689A1
公开(公告)日：2008-06-05
申请号：US11947725
申请日：2007-11-29
申请人： Je-hun Lee , Dong-ju Yang , Tae-hyung Ihn , Do-hyun Kim , Sun-young Hong , Seung-jae Jung , Chang-oh Jeong , Eun-guk Lee
发明人： Je-hun Lee , Dong-ju Yang , Tae-hyung Ihn , Do-hyun Kim , Sun-young Hong , Seung-jae Jung , Chang-oh Jeong , Eun-guk Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7869
摘要： Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.
摘要翻译：提供一种制造半导体氧化物薄膜晶体管（TFT）衬底的方法。该方法包括在绝缘基板上形成栅极布线; 并且形成其中半导体氧化物膜图案和数据布线堆叠在栅极布线上的结构，其中半导体氧化物膜图案被选择性地图案化以具有第二厚度的第一厚度的沟道区域和源极/漏极区域，并且其中图像数据通过形成在源极区域上的数据布线耦合到源极区域。根据4掩模实施例，数据布线和半导体氧化膜图案由共享蚀刻掩模限定。

32. 发明申请

US20050199186A1 Inductively coupled plasma apparatus using magnetic field 审中-公开
标题翻译：使用磁场的感应耦合等离子体装置
公开(公告)号：US20050199186A1
公开(公告)日：2005-09-15
申请号：US10914167
申请日：2004-08-10
申请人： Geun-Young Yeom , Kyong-nam Kim , Seung-jae Jung
发明人： Geun-Young Yeom , Kyong-nam Kim , Seung-jae Jung
IPC分类号： C23C16/00
CPC分类号： H01J37/3211 , H01J37/321 , H01J37/32669
摘要： Disclosed is an inductively coupled plasma apparatus using a magnetic field. The inductively coupled plasma apparatus comprises a reaction chamber in which a substrate is loaded, an antenna source installed in the reaction chamber and including first and second antennas having antenna rods, which are alternately aligned, and magnets installed above the antenna rods, wherein first sides of the first and second antennas are connected to a power source and second sides of the first and second antennas are grounded. Plasma uniformity is improved and superior plasma uniformity is maintained by adjusting a distance between antennas according to a size of the substrate.
摘要翻译：公开了使用磁场的电感耦合等离子体装置。电感耦合等离子体装置包括反应室，其中装载有基板，安装在反应室中的天线源，并且包括交替对准的具有天线杆的第一和第二天线以及安装在天线杆上方的磁体，其中第一侧的第一和第二天线连接到电源，第一和第二天线的第二侧接地。等离子体均匀性得到改善，并且通过根据基板的尺寸调节天线之间的距离来维持优异的等离子体均匀性。

33. 发明申请

US20180350830A1 SEMICONDUCTOR DEVICE INCLUDING INSULATING LAYERS AND METHOD OF FORMING THE SAME 审中-公开
公开(公告)号：US20180350830A1
公开(公告)日：2018-12-06
申请号：US15816638
申请日：2017-11-17
申请人： YEONG DAE LIM , SEUNG JAE JUNG , JIN YOUNG BANG , IL WOO KIM , HO GIL JUNG
发明人： YEONG DAE LIM , SEUNG JAE JUNG , JIN YOUNG BANG , IL WOO KIM , HO GIL JUNG
IPC分类号： H01L27/11582 , H01L29/06 , H01L27/11568 , H01L29/10
CPC分类号： H01L27/11582 , H01L21/0217 , H01L21/02211 , H01L21/02271 , H01L21/0228 , H01L21/02532 , H01L21/02595 , H01L21/02636 , H01L21/28282 , H01L21/31111 , H01L27/11565 , H01L27/11568 , H01L29/0657 , H01L29/1037
摘要： A semiconductor device includes a substrate, a stacked structure of insulating layers and gate electrodes alternately and repeatedly stacked on the substrate, and a pillar passing through the stacked-layer structure. The insulating layers include lower insulating layers, intermediate insulating layers disposed on the lower insulating layers, and upper insulating layers disposed on the intermediate insulating layers. The lower insulating layers have a hardness less than that of the intermediate insulating layers, and the upper insulating layers have a hardness greater than that of the intermediate insulating layers.

34. 发明授权

US09812501B2 Variable resistance memory devices and methods of manufacturing the same 有权
公开(公告)号：US09812501B2
公开(公告)日：2017-11-07
申请号：US14984477
申请日：2015-12-30
申请人： Jin-Woo Lee , Youn-Seon Kang , Seung-Jae Jung , Hyun-Su Ju , Masayuki Terai
发明人： Jin-Woo Lee , Youn-Seon Kang , Seung-Jae Jung , Hyun-Su Ju , Masayuki Terai
IPC分类号： H01L27/24 , H01L43/08 , H01L43/02 , H01L43/12 , H01L45/00 , H01L27/22
CPC分类号： H01L27/2463 , H01L27/224 , H01L27/2409 , H01L43/12 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

35. 发明申请

US20160197121A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20160197121A1
公开(公告)日：2016-07-07
申请号：US14984477
申请日：2015-12-30
申请人： Jin-Woo LEE , Youn-Sean KANG , Seung-Jae JUNG , Hyun-Su JU , Masayuki TERAI
发明人： Jin-Woo LEE , Youn-Sean KANG , Seung-Jae JUNG , Hyun-Su JU , Masayuki TERAI
IPC分类号： H01L27/24 , H01L43/08 , H01L43/02 , H01L45/00 , H01L27/22
CPC分类号： H01L27/2463 , H01L27/224 , H01L27/2409 , H01L43/12 , H01L45/1675
摘要： A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.
摘要翻译：可变电阻存储器件包括多个第一导电层图案，多个第一导电层图案上的第二导电层图案，以及包括开关元件和可变电阻元件的多个下单元结构，下单元结构为形成在第一导电层图案和第二导电层图案彼此重叠的交点处。第一导电层图案，第二导电层图案和下单元结构用作存储单元，第一虚设图案结构和第二虚设图案结构之一。第一虚设图形结构形成在第一方向的两个边缘部分上，第一虚设图案结构的第二导电层图案从其下部单元结构的侧壁沿第一方向突出，第二虚设图案结构为形成在第二方向的两个边缘部分上，并且第二虚设图案结构的第一导电层图案在其下面的单元结构的侧壁上沿第二方向突出。由于蚀刻残留导致的可变电阻存储器件的故障可能降低。

36. 发明申请

US20160049447A1 RESISTIVE MEMORY DEVICE AND METHOD OF OPERATING RESISTIVE MEMORY DEVICE 有权
标题翻译：电阻式存储器件和操作电阻式存储器件的方法
公开(公告)号：US20160049447A1
公开(公告)日：2016-02-18
申请号：US14736525
申请日：2015-06-11
申请人： SEUNG-JAE JUNG , YOUN-SEON KANG , JUNG-DAL CHOI
发明人： SEUNG-JAE JUNG , YOUN-SEON KANG , JUNG-DAL CHOI
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/224 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A resistive memory device includes a plurality of memory cell pillars arranged in a line in one direction and each having a memory layer and a top electrode layer connected to the memory layer, a top conductive line having a plurality of protrusions extending downwardly and between which pockets in the bottom of the top conductive line are defined, and a plurality of insulating pillars. The protrusions of the top conductive line face and are electrically connected to the memory cell pillars, respectively, so as to be electrically connected to the memory layer through the top electrode layer of the memory cell pillar. The insulating pillars extend from insulating spaces, between side wall surfaces of the memory layers and top electrode layers of the memory cell pillars, into the pockets in the bottom of the top conductive line.
摘要翻译：电阻式存储器件包括沿一个方向排列成一行的多个存储器单元柱，每个存储单元柱具有连接到存储层的存储层和顶部电极层，顶部导电线具有向下延伸的多个突起，在顶部导线的底部被限定，以及多个绝缘柱。上导电线面的突起分别电连接到存储单元柱，以便通过存储单元柱的顶电极电连接到存储层。绝缘柱从记忆层的侧壁表面和存储单元柱的顶部电极层之间的绝缘空间延伸到顶部导电线的底部中的凹穴中。

37. 发明申请

US20160027845A1 VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：可变电阻存储器件及其制造方法
公开(公告)号：US20160027845A1
公开(公告)日：2016-01-28
申请号：US14682506
申请日：2015-04-09
申请人： Dong-Jun SEONG , Youn-Seon KANG , Seung-Jae JUNG , Jung-Dal CHOI
发明人： Dong-Jun SEONG , Youn-Seon KANG , Seung-Jae JUNG , Jung-Dal CHOI
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2463 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.
摘要翻译：可变电阻存储器件及其制造方法包括沿第一方向延伸的多个第一导电结构，沿与第一导电结构相交的第一方向的第二方向延伸的多个第二导电结构，第二导电结构和形成在第一导电结构和第二导电结构彼此重叠的交点处的多个存储单元，并且每个存储单元包括依次堆叠的选择元件和可变电阻元件。每个第一导电结构的上表面在第二方向上的宽度小于每个选择元件的底表面的宽度。

38. 发明授权

US08802972B2 Photoelectric conversion device and manufacturing method thereof 有权
标题翻译：光电转换装置及其制造方法
公开(公告)号：US08802972B2
公开(公告)日：2014-08-12
申请号：US12476645
申请日：2009-06-02
申请人： Min-Seok Oh , Jung-Tae Kim , Nam-Kyu Song , Min Park , Yun-Seok Lee , Czang-Ho Lee , Myung-Hun Shin , Byoung-Kyu Lee , Yuk-Hyun Nam , Seung-Jae Jung , Mi-Hwa Lim , Joon-Young Seo , Dong-Uk Choi , Dong-Seop Kim , Byoung-June Kim
发明人： Min-Seok Oh , Jung-Tae Kim , Nam-Kyu Song , Min Park , Yun-Seok Lee , Czang-Ho Lee , Myung-Hun Shin , Byoung-Kyu Lee , Yuk-Hyun Nam , Seung-Jae Jung , Mi-Hwa Lim , Joon-Young Seo , Dong-Uk Choi , Dong-Seop Kim , Byoung-June Kim
IPC分类号： H01L31/0224 , H01L31/0376 , H01L31/0368 , H01L31/068 , H01L31/078
CPC分类号： H01L31/022441 , H01L31/022425 , H01L31/022466 , H01L31/02363 , H01L31/03682 , H01L31/03762 , H01L31/068 , H01L31/0682 , H01L31/072 , H01L31/078 , H01L31/182 , Y02E10/52 , Y02E10/547 , Y02E10/548
摘要： Disclosed herein is a photoelectric conversion device having a semiconductor substrate including a front side and back side, a protective layer formed on the front side of the semiconductor substrate, a first non-single crystalline semiconductor layer formed on the back side of the semiconductor substrate, a first conductive layer including a first impurity formed on a first portion of a back side of the first non-single crystalline semiconductor layer, and a second conductive layer including the first impurity and a second impurity formed on a second portion of the back side of the first non-single crystalline semiconductor layer.
摘要翻译：这里公开了一种光电转换装置，其具有包括正面和背面的半导体衬底，形成在半导体衬底的正面上的保护层，形成在半导体衬底背面的第一非单晶半导体层，第一导电层，包括形成在第一非单晶半导体层的背面的第一部分上的第一杂质，以及第二导电层，其包含第一杂质和第二杂质，所述第二杂质形成在第一非杂质半导体层的背面的第二部分上第一非单晶半导体层。

39. 发明申请

US20130045564A1 Method of manufacturing a photovoltaic device 审中-公开
标题翻译：制造光伏器件的方法
公开(公告)号：US20130045564A1
公开(公告)日：2013-02-21
申请号：US13655511
申请日：2012-10-19
申请人： Min PARK , Min-Seok OH , Jung-Tae KIM , Czang-Ho LEE , Myung-Hun SHIN , Byoung-Kyu LEE , Ku-Hyun KANG , Yuk-Hyun NAM , Seung-Jae JUNG , Mi-Hwa LIM , Joon-Young SEO
发明人： Min PARK , Min-Seok OH , Jung-Tae KIM , Czang-Ho LEE , Myung-Hun SHIN , Byoung-Kyu LEE , Ku-Hyun KANG , Yuk-Hyun NAM , Seung-Jae JUNG , Mi-Hwa LIM , Joon-Young SEO
IPC分类号： H01L31/02
CPC分类号： H01L31/075 , H01L31/022441 , H01L31/046 , Y02E10/548
摘要： A photovoltaic device and a manufacturing method thereof are provided. The photovoltaic device includes: a substrate; a first conductive layer formed on the substrate; P layers and N layers alternately formed along a first direction on the first conductive layer; and I layers covering the P layers and the N layers on the first conductive layer, wherein the P layers and the N layers are separated from each other by a first interval, the I layers are formed between the P layers and the N layers that are separated by the first interval, and the P layers, the I layers, and the N layers formed along the first direction form unit cells.
摘要翻译：提供了一种光电器件及其制造方法。光电器件包括：基板; 形成在所述基板上的第一导电层; 在第一导电层上沿着第一方向交替形成P层和N层; I层覆盖第一导电层上的P层和N层，其中P层和N层彼此分开第一间隔，I层形成在P层与N层之间分离第一间隔，并且沿着第一方向形成的P层，I层和N层形成单位电池。

40. 发明授权

US08354585B2 Solar cell and method of fabricating the same 失效
标题翻译：太阳能电池及其制造方法
公开(公告)号：US08354585B2
公开(公告)日：2013-01-15
申请号：US12582037
申请日：2009-10-20
申请人： Min-Seok Oh , Byoung-Kyu Lee , Min Park , Czang-Ho Lee , Myung-Hun Shin , Yuk-Hyun Nam , Seung-Jae Jung , Mi-Hwa Lim , Joon-Young Seo
发明人： Min-Seok Oh , Byoung-Kyu Lee , Min Park , Czang-Ho Lee , Myung-Hun Shin , Yuk-Hyun Nam , Seung-Jae Jung , Mi-Hwa Lim , Joon-Young Seo
IPC分类号： H01L31/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/0236 , H01L31/02363 , H01L31/03529 , H01L31/0745 , H01L31/0747 , Y02E10/547
摘要： A solar cell includes: a semiconductor substrate having a first surface and a second surface opposite the first surface; uneven patterns disposed on at least one of the first surface and the second surface of the semiconductor substrate; a first impurity layer disposed on the uneven patterns and which includes a first part having a first doping concentration and a second part having a second doping concentration greater than the first doping concentration; and a first electrode which contacts the second part of the first impurity layer and does not contact the first part of the first impurity layer.
摘要翻译：太阳能电池包括：具有第一表面和与第一表面相对的第二表面的半导体衬底; 设置在半导体衬底的第一表面和第二表面中的至少一个上的不均匀图案; 设置在所述凹凸图案上的第一杂质层，其包括具有第一掺杂浓度的第一部分和具有大于所述第一掺杂浓度的第二掺杂浓度的第二部分; 以及与第一杂质层的第二部分接触并且不接触第一杂质层的第一部分的第一电极。

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