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31. 发明申请

WO2008016849A2 METHOD AND APPARATUS FOR PREFETCHING NON-SEQUENTIAL INSTRUCTION ADDRESSES 审中-公开
标题翻译：用于推荐非序列指令地址的方法和装置
公开(公告)号：WO2008016849A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074598
申请日：2007-07-27
申请人： QUALCOMM Incorporated , STEMPEL, Brian, Michael , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne
发明人： STEMPEL, Brian, Michael , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

32. 发明申请

WO2007124307A3 VIRTUALLY-TAGGED INSTRUCTION CACHE WITH PHYSICALLY-TAGGED BEHAVIOR 审中-公开
标题翻译：带有物理标签行为的VIRTUALLY-TAGGED指令高速缓存
公开(公告)号：WO2007124307A3
公开(公告)日：2007-12-27
申请号：PCT/US2007066802
申请日：2007-04-17
申请人： QUALCOMM INC , SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STREETT DAREN EUGENE
发明人： SARTORIUS THOMAS ANDREW , SMITH RODNEY WAYNE , STREETT DAREN EUGENE
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/1063 , G06F12/0891 , G06F2212/1056 , G06F2212/683
摘要： An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
摘要翻译：一种具有虚拟标记的指令高速缓存的指令高速缓存系统，其从软件程序的角度来看，如同它是物理标记的指令高速缓存一样被操作。指令高速缓存系统还包括响应于地址转换无效指令和控制逻辑电路的地址转换装置。控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

33. 发明申请

WO2007133895A1 BLOCK-BASED BRANCH TARGET ADDRESS CACHE 审中-公开
标题翻译：基于块的分支目标地址高速缓存
公开(公告)号：WO2007133895A1
公开(公告)日：2007-11-22
申请号：PCT/US2007/067176
申请日：2007-04-23
申请人： QUALCOMM Incorporated , SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
发明人： SMITH, Rodney Wayne , DIEFFENDERFER, James Norris , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/3836
摘要： A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken branch instruction. The BTAC entry also includes the Branch Target Address (BTA) of the taken branch. The block size may, but does not necessarily, correspond to the number of instructions per instruction cache line.
摘要翻译：分支目标地址缓存（BTAC）存储多个条目，每个BTAC条目与包括已经被评估的至少一个分支指令的两个或更多个指令的块相关联。 BTAC条目包括关联块内哪个指令是采取的分支指令的指示符。 BTAC条目还包括采集分支的分行目标地址（BTA）。块大小可以但不一定对应于每条指令高速缓存线的指令数。

34. 发明申请

WO2007048136B1 METHOD AND APPARATUS TO CLEAR SEMAPHORE RESERVATION 审中-公开
标题翻译：方法和装置清除SEMAPHORE预留
公开(公告)号：WO2007048136B1
公开(公告)日：2007-08-09
申请号：PCT/US2006060136
申请日：2006-10-20
申请人： QUALCOMM INC , SPEIER THOMAS PHILIP , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , GANASAN JAYA PRAKASH SUBRAMANI
发明人： SPEIER THOMAS PHILIP , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , GANASAN JAYA PRAKASH SUBRAMANI
IPC分类号： G06F9/46
CPC分类号： G06F9/526
摘要： Semaphore (116) operation manages exclusive access to a memory (114) that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is (102a), (102b) monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller (104) is changed from a reservation state to a non-reservation state in response to receipt of the command signal.
摘要翻译：信号量（116）操作管理对由多个处理元件共享的存储器（114）的独占访问。由处理元件进行排他访问的信号量预留状态是由存储器控制器监视的（102a），（102b）。为了清除过时的预约状态，在禁止更新存储器的内容的同时，向存储器发送用于写入操作的命令信号。响应于接收到命令信号，控制器（104）的预约状态从预约状态改变为非预约状态。

35. 发明申请

WO2007085011A2 EFFICIENT MEMORY HIERARCHY MANAGEMENT 审中-公开
标题翻译：有效的记忆层级管理
公开(公告)号：WO2007085011A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060815
申请日：2007-01-22
申请人： QUALCOMM INCORPORATED , MORROW, Michael William , SARTORIUS, Thomas Andrew
发明人： MORROW, Michael William , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F12/0848
摘要： In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.
摘要翻译：在处理器中，在执行程序之前，存在指令和程序的某些部分可能驻留在数据高速缓存中的情况。提供硬件和软件技术，用于在指令高速缓存中未命中以提高处理器性能之后在数据高速缓存中获取指令。如果指令缓存中没有指令，则指令提取地址作为数据提取地址发送到数据缓存。如果在提供的取指地址的数据高速缓存中存在有效数据，则数据实际上是一条指令，并且数据高速缓存条目被提取并作为指令提供给处理器组合系统。指令页表中可能包含一个额外的位，以指示指令缓存中的未命中数据缓存应该检查该指令。

36. 发明申请

WO2007016393A3 INSTRUCTION CACHE HAVING FIXED NUMBER OF VARIABLE LENGTH INSTRUCTIONS 审中-公开
标题翻译：指令缓存具有固定数量的可变长度指令
公开(公告)号：WO2007016393A3
公开(公告)日：2007-06-28
申请号：PCT/US2006029523
申请日：2006-07-26
申请人： QUALCOMM INC , BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
发明人： BRIDGES JEFFREY TODD , DIEFFENDERFER JAMES NORRIS , SMITH RODNEY WAYNE , SARTORIUS THOMAS ANDREW
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/382
摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.
摘要翻译：固定数量的可变长度指令存储在指令高速缓存的每一行中。可变长度指令沿着预定的边界对齐。由于该行中每条指令的长度以及指令占用的内存范围是未知的，因此下一条指令的地址将被计算并与高速缓存行一起存储。在将指令放置在高速缓存中之前，在预解码器中执行确定指令边界，对齐指令以及计算下一个提取地址。

37. 发明申请

WO2007048136A2 METHOD AND APPARATUS TO CLEAR SEMAPHORE RESERVATION 审中-公开
标题翻译：清除SEMAPHORE预留的方法和装置
公开(公告)号：WO2007048136A2
公开(公告)日：2007-04-26
申请号：PCT/US2006060136
申请日：2006-10-20
申请人： QUALCOMM INC , SPEIER THOMAS PHILIP , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , GANASAN JAYA PRAKASH SUBRAMANI
发明人： SPEIER THOMAS PHILIP , DIEFFENDERFER JAMES NORRIS , SARTORIUS THOMAS ANDREW , GANASAN JAYA PRAKASH SUBRAMANI
CPC分类号： G06F9/526
摘要： Semaphore operation manages exclusive access to a memory that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller is changed from a reservation state to a non-reservation state in response to receipt of the command signal.
摘要翻译：信号量操作管理对由多个处理元件共享的存储器的独占访问。由处理元件独占访问的信号量预留状态由存储器控制器监视。为了清除过时的预约状态，在禁止更新存储器的内容的同时，向存储器发送用于写入操作的命令信号。响应于接收到命令信号，控制器的预约状态从预约状态改变为非预约状态。

38. 发明申请

WO2007048135A1 CACHING MEMORY ATTRIBUTE INDICATORS WITH CACHED MEMORY DATA 审中-公开
标题翻译：具有缓存存储器数据的缓存内存分配指示器
公开(公告)号：WO2007048135A1
公开(公告)日：2007-04-26
申请号：PCT/US2006/060135
申请日：2006-10-20
申请人： QUALCOMM Incorporated , BRIDGES, Jeffrey, Todd , DIEFFENDERFER, James, Norris , SARTORIUS, Thomas, Andrew , STEMPEL, Brian, Michael , SMITH, Rodney, Wayne
发明人： BRIDGES, Jeffrey, Todd , DIEFFENDERFER, James, Norris , SARTORIUS, Thomas, Andrew , STEMPEL, Brian, Michael , SMITH, Rodney, Wayne
IPC分类号： G06F12/10
CPC分类号： G06F12/1063 , G06F12/1054 , G06F12/145 , Y02D10/13
摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.
摘要翻译：处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。存储器中的每个页面可以包括多行存储器。当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存行具有与虚拟地址匹配的匹配地址。存储器高速缓存可以被配置为允许通过在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索，的数据存储在缓存行中。

39. 发明申请

WO2007048134A1 UPDATING MULTIPLE LEVELS OF TRANSLATION LOOKASIDE BUFFERS (TLBS) FIELD 审中-公开
标题翻译：更新多层次的翻译LOOKASIDE BUFFERS（TLBS）领域
公开(公告)号：WO2007048134A1
公开(公告)日：2007-04-26
申请号：PCT/US2006/060134
申请日：2006-10-20
申请人： QUALCOMM INCORPORATED , AUGSBURG, Victor Roberts , SARTORIUS, Thomas Andrew , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd
发明人： AUGSBURG, Victor Roberts , SARTORIUS, Thomas Andrew , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.
摘要翻译：一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。

40. 发明申请

WO2007035904A1 METHOD AND APPARATUS FOR MANAGING CACHE PARTITIONING 审中-公开
标题翻译：管理缓存分区的方法和设备
公开(公告)号：WO2007035904A1
公开(公告)日：2007-03-29
申请号：PCT/US2006/036938
申请日：2006-09-21
申请人： QUALCOMM INCORPORATED , STEMPEL, Brian, Michael , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne , CLANCY, Robert, Douglas , AUGSBURG, Victor, Roberts
发明人： STEMPEL, Brian, Michael , DIEFFENDERFER, James, Norris , BRIDGES, Jeffrey, Todd , SARTORIUS, Thomas, Andrew , SMITH, Rodney, Wayne , CLANCY, Robert, Douglas , AUGSBURG, Victor, Roberts
IPC分类号： G06F12/12
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the first pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级的写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，第一指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

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