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31. 发明授权

US06484240B1 Mechanism for reordering transactions in computer systems with snoop-based cache consistency protocols 有权
标题翻译：使用基于snoop的缓存一致性协议重新排序计算机系统中的事务的机制
公开(公告)号：US06484240B1
公开(公告)日：2002-11-19
申请号：US09365159
申请日：1999-07-30
申请人： Robert Cypher , Ricky C. Hetherington , Belliappa Kuttanna
发明人： Robert Cypher , Ricky C. Hetherington , Belliappa Kuttanna
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： An apparatus and method for expediting the processing of requests in a multiprocessor shared memory system. In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed. First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor. Second, all requests that reference the same cache line are processed in the order in which they arrive. In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated. In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data. In addition, newer local requests can be processed before older local requests. As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol.
摘要翻译：一种用于加速处理多处理器共享存储器系统中的请求的装置和方法。在多处理器共享存储器系统中，可以按照遵循的两个规则的任何顺序处理请求。首先，在从处理器撤销访问权限的较旧请求之前，不能处理授予处理器访问权限的请求。其次，引用同一个高速缓存行的所有请求按照它们到达的顺序进行处理。以这种方式，请求可以被无序地处理，以允许缓存到缓存传输被加速。特别地，要求处理器提供数据的外部请求可以在等待数据的较早的本地请求之前被该处理器处理。此外，较旧的本地请求可以在较旧的本地请求之前处理。结果，本文描述的装置和方法可以有利地通过减少与高速缓存一致性协议相关联的延迟来增加多处理器共享存储器系统中的性能。

32. 发明授权

US06304992B1 Technique for correcting single-bit errors in caches with sub-block parity bits 有权
标题翻译：用于校正具有子块奇偶校验位的高速缓存中的单位错误的技术
公开(公告)号：US06304992B1
公开(公告)日：2001-10-16
申请号：US09160214
申请日：1998-09-24
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M1300
CPC分类号： G06F11/1064 , G06F11/1012
摘要： A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits. Accordingly, the sub-block and the bit position within the sub-block may be detected by using the sub-block check bits and the composite check bits.
摘要翻译：数据块包括多个子块。每个子块包括可以用于检测子块内的位错误的存在的子块校验位。生成复合子块，其是每个子块的列逐排或比特。在一个实施例中，复合子块不被存储，而是仅用于计算目的。多个复合校验位用于检测复合子块内的位错误的位位置。如果发生数据块内的位错误，则可以使用子块校验位来检测发生错误的子块。复合校验位可用于确定复合子块的哪个位位置是错误的。复合子块的错误位位置还标识由子块校验位识别的子块中的错误位的位位置。因此，可以通过使用子块校验位和复合校验位来检测子块内的子块和比特位置。

33. 发明授权

US06282686B1 Technique for sharing parity over multiple single-error correcting code words 有权
标题翻译：通过多个单纠错码字共享奇偶校验的技术
公开(公告)号：US06282686B1
公开(公告)日：2001-08-28
申请号：US09160771
申请日：1998-09-24
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M1300
CPC分类号： G06F11/1028
摘要： The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. Each logical group uses a single error correcting code to detect and correct bit errors. A parity bit is appended to a data block that includes a plurality of logical groups. The parity bit may be used in conjunction with the single error correcting codes to determine whether a detected error is a single bit error or a multiple bit error. If the detected error is a single bit error, the error correction codes may be used to correct the error. If the detected error is a multiple bit error, an uncorrectable error may be reported.
摘要翻译：将数据块的比特分配给多个逻辑组，使得至多一个对应于分量的比特被分配给逻辑组。此分配确保组件故障最多可能向逻辑组引入一个位错误。每个逻辑组使用单个纠错码来检测和纠正位错误。奇偶校验位附加到包括多个逻辑组的数据块。奇偶校验位可以与单个纠错码结合使用，以确定检测到的错误是单位错误还是多位错误。如果检测到的错误是单位错误，则纠错码可用于纠正错误。如果检测到的错误是多位错误，则可能会报告不可纠正的错误。

34. 发明授权

US08719675B1 Orthogonal coding for data storage, access, and maintenance 有权
标题翻译：用于数据存储，访问和维护的正交编码
公开(公告)号：US08719675B1
公开(公告)日：2014-05-06
申请号：US12880372
申请日：2010-09-13
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H03M13/2909 , H03M13/1515 , H03M13/2918
摘要： Methods, systems, and apparatus, including computer program products, for orthogonal coding for data storage. In one aspect, a method includes receiving a block of data comprising m rows and n columns of data chunks. For each row in the block of data, (c-n) columns of error-correcting row code chunks are generated using a first linear error-correcting code in systematic form and the particular row's data chunks. For each column in the block of data and for each generated column, particular column and (r-m) error-correcting column code chunks for the particular column are allocated to a distinct group of storage nodes, wherein: the column code chunks are generated using a second linear error-correcting code in systematic form and the particular column's data chunks or row code chunks; m and n are greater than one; and c is greater than n and r is greater than m.
摘要翻译：用于数据存储的正交编码的方法，系统和装置，包括计算机程序产品。在一个方面，一种方法包括接收包括m行和n列的数据块的数据块。对于数据块中的每一行，使用系统形式的第一线性纠错码和特定行的数据块生成错误校正行代码块的（c-n）列。对于数据块和每个生成的列中的每一列，特定列的特定列和（rm）纠错列代码块被分配给不同的存储节点组，其中：列代码块使用系统形式的第二个线性纠错码和特定列的数据块或行代码块; m和n大于1; 并且c大于n且r大于m。

35. 发明授权

US08640000B1 Nested coding techniques for data storage 有权
标题翻译：用于数据存储的嵌套编码技术
公开(公告)号：US08640000B1
公开(公告)日：2014-01-28
申请号：US13162191
申请日：2011-06-16
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H03M13/00
CPC分类号： H03M13/2909 , H03M13/1515 , H03M13/2918
摘要： Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first linear error-correcting code in systematic form and the data chunks. For each of m rows of the data chunks, one or more split row code chunks are generated using the data chunks of the row, wherein the split row code chunks are generated so that a linear combination of m split row code chunks from different rows forms a first word code chunk of a first codeword including the data chunks and the word code chunks. The rows of data chunks and the split row code chunks and the word code chunks are stored.
摘要翻译：方法，系统和装置，包括在计算机存储介质上编码的计算机程序，用于偏斜正交编码技术。一方面，一种方法包括接收包括多个数据块的数据块。使用系统形式的第一线性纠错码和数据块来生成一行或多行字代码块。对于m行的数据块中的每一行，使用行的数据块生成一个或多个分割行代码块，其中生成分割行代码块，使得来自不同行的m个拆分行代码块的线性组合形成包括数据块和字代码块的第一码字的第一字代码块。存储数据块和拆分行代码块和字代码块的行。

36. 发明申请

US20100161904A1 CACHE HIERARCHY WITH BOUNDS ON LEVELS ACCESSED 有权
标题翻译： CACHE层次结合层次上的界限
公开(公告)号：US20100161904A1
公开(公告)日：2010-06-24
申请号：US12343065
申请日：2008-12-23
申请人： Robert Cypher , Haakan Zeffer , Anders Landin
发明人： Robert Cypher , Haakan Zeffer , Anders Landin
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0862
摘要： The present invention is directed to a system managing data in a multilevel cache memory system. Certain cache data is designated and stored only in particular levels of the multilevel cache, bypassing other levels of the multilevel cache. In a multiprocessor environment, the present invention includes cache coherency operations or messages that pertain to data stored only in certain levels of a multilevel cache.
摘要翻译：本发明涉及一种管理多级高速缓冲存储器系统中的数据的系统。某些高速缓存数据被指定并仅存储在多级缓存的特定级别中，从而绕过多级高速缓存的其他级别。在多处理器环境中，本发明包括高速缓存一致性操作或与仅存储在多级缓存的特定级别中的数据相关的消息。

37. 发明申请

US20060107024A1 Mechanism and method for determining stack distance of running software 有权
标题翻译：确定运行软件堆栈距离的机制和方法
公开(公告)号：US20060107024A1
公开(公告)日：2006-05-18
申请号：US11281733
申请日：2005-11-16
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F12/10
CPC分类号： G06F11/3616 , G06F12/0802
摘要： A method and apparatus for determining a stack distance histogram for running software. The method may include receiving a plurality of memory references each including a corresponding address. The method may also include performing a first hash function and a second hash function on each received address. In addition, the method may include selectively storing an indication representative of each corresponding address in a hash table dependent upon results of the first hash function and the second hash function. A stack distance may then be determined based upon contents of the hash table.
摘要翻译：一种用于确定运行软件的堆栈距离直方图的方法和装置。该方法可以包括接收多个存储器引用，每个存储器引用包括对应的地址。该方法还可以包括对每个接收到的地址执行第一散列函数和第二散列函数。此外，该方法可以包括：依赖于第一散列函数和第二散列函数的结果，选择性地将表示每个对应地址的指示存储在散列表中。然后可以基于散列表的内容来确定堆栈距离。

38. 发明授权

US06901495B2 Cache memory system allowing concurrent reads and writes to cache lines to increase snoop bandwith 有权
标题翻译：高速缓存存储器系统允许并发读取和写入高速缓存行以增加窥探带宽
公开(公告)号：US06901495B2
公开(公告)日：2005-05-31
申请号：US10673654
申请日：2003-09-29
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0846 , G06F12/0831 , G06F12/0851
摘要： A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors. The cache controller is configured to concurrently access the cache tags of multiple lines in response to the snoop requests if the lines correspond to differing classes.
摘要翻译：高速缓冲存储器包括多个存储器芯片或其它单独可寻址的存储器部分，其被配置为共同存储多个高速缓存线。每个缓存行包括数据和关联的高速缓存标签。高速缓存标签可以包括标识行的地址标签以及指示该行的一致性状态的状态信息。每个高速缓存行被存储在由对应条目形成的行中的存储器芯片（即，使用相同的索引地址访问的条目）中。多个高速缓存行基于索引地址被分组成单独的子集，从而形成几个单独的高速缓存行类别。与不同类别的高速缓存行相关联的缓存标签被存储在不同的存储器芯片中。在操作期间，高速缓存控制器可以接收与例如由各种处理器发起的事务相对应的多个窥探请求。缓存控制器被配置为如果行对应于不同的类，则响应于窥探请求同时访问多行的高速缓存标签。

39. 发明申请

US20050013294A1 Multi-node computer system with active devices employing promise arrays for outstanding transactions 审中-公开
标题翻译：具有活动设备的多节点计算机系统，采用承诺阵列进行未完成的交易
公开(公告)号：US20050013294A1
公开(公告)日：2005-01-20
申请号：US10814089
申请日：2004-03-31
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： H04L12/56 , H04L29/08
CPC分类号： G06F12/0817 , G06F12/0831 , H04L67/10
摘要： A node for use in a multi-node computer system includes: a plurality of active devices; an interface configured to send and receive coherency messages on an inter-node network coupling nodes in the multi-node computer system; an address network configured to communicate address packets between the active devices and the interface; and a data network configured to communicate data packets between the active devices and the interface. The active device includes a promise array configured to store a promise identifying a data packet to be conveyed to a device in response to a pending local transaction involving a coherency unit for which the active device has an ownership responsibility. The active device is configured to store promises in the promise array in response to receiving address packets from other ones of the plurality of active devices and from the interface.
摘要翻译：用于多节点计算机系统的节点包括：多个有源设备; 接口，被配置为在耦合所述多节点计算机系统中的节点的节点间网络上发送和接收一致性消息; 地址网络，被配置为在所述活动设备和所述接口之间传送地址分组; 以及数据网络，被配置为在活动设备和接口之间传送数据分组。活动设备包括承诺阵列，其被配置为响应于涉及有源设备具有所有权责任的一致性单元的待决本地事务来存储识别要传送到设备的数据分组的承诺。活动设备被配置为响应于从多个活动设备中的其他主动设备接收的地址分组和从接口接收地址分组来在承诺阵列中存储承诺。

40. 发明授权

US06629205B2 System and method for increasing the snoop bandwidth to cache tags in a cache memory subsystem 有权
标题翻译：将侦听带宽增加到高速缓存存储器子系统中的缓存标签的系统和方法
公开(公告)号：US06629205B2
公开(公告)日：2003-09-30
申请号：US09792103
申请日：2001-02-23
申请人： Robert Cypher
发明人： Robert Cypher
IPC分类号： G06F1208
CPC分类号： G06F12/0846 , G06F12/0831 , G06F12/0851
摘要： A cache memory includes a plurality of memory chips, or other separately addressable memory sections, which are configured to collectively store a plurality of cache lines. Each cache line includes data and an associated cache tag. The cache tag may include an address tag which identifies the line as well as state information indicating the coherency state for the line. Each cache line is stored across the memory chips in a row formed by corresponding entries (i.e., entries accessed using the same index address). The plurality of cache lines is grouped into separate subsets based on index addresses, thereby forming several separate classes of cache lines. The cache tags associated with cache lines of different classes are stored in different memory chips. During operation, the cache controller may receive multiple snoop requests corresponding to, for example, transactions initiated by various processors. The cache controller is configured to concurrently access the cache tags of multiple lines in response to the snoop requests if the lines correspond to differing classes.
摘要翻译：高速缓冲存储器包括多个存储器芯片或其它单独可寻址的存储器部分，其被配置为共同存储多个高速缓存线。每个缓存行包括数据和关联的高速缓存标签。高速缓存标签可以包括标识行的地址标签以及指示该行的一致性状态的状态信息。每个高速缓存行被存储在由对应条目形成的行中的存储器芯片（即，使用相同的索引地址访问的条目）中。多个高速缓存行基于索引地址被分组成单独的子集，从而形成几个单独的高速缓存行类别。与不同类别的高速缓存行相关联的缓存标签被存储在不同的存储器芯片中。在操作期间，高速缓存控制器可以接收与例如由各种处理器发起的事务相对应的多个窥探请求。缓存控制器被配置为如果行对应于不同的类，则响应于窥探请求同时访问多行的高速缓存标签。

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