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31. 发明授权

US08368422B1 System and method for testing off-chip driver impedance 有权
标题翻译：用于测试片外驱动器阻抗的系统和方法
公开(公告)号：US08368422B1
公开(公告)日：2013-02-05
申请号：US13463832
申请日：2012-05-04
申请人： Bret Roberts Dale , Oliver Kiehl
发明人： Bret Roberts Dale , Oliver Kiehl
IPC分类号： H03K19/00
CPC分类号： H03K5/1534 , H03K19/00346
摘要： A testing circuit for verifying the impedance of off-chip drivers includes: a plurality of off-chip drivers (OCD), each off-chip driver including a through-silicon via (TSV); an IREF test pad, for driving a current to the plurality of off-chip drivers; a plurality of pre-drivers, each respective pre-driver coupled to one of the plurality of off-chip drivers, wherein the plurality of pre-drivers are configured to turn on the off-chip drivers; a VREF test pad, for inputting a reference voltage to the testing circuit; a plurality of input buffers (IB) for outputting a plurality of comparison results, each of the plurality of input buffers configured to output the plurality of comparison results according to the reference voltage and the voltage at the TSV nodes; and a test pad, coupled to the plurality of IBs, for receiving the comparison results to determine whether the impedance of each OCD is within a desired range.
摘要翻译：用于验证片外驱动器的阻抗的测试电路包括：多个芯片外驱动器（OCD），每个芯片外驱动器包括穿硅通孔（TSV）; 用于驱动电流到所述多个芯片外驱动器的IREF测试焊盘; 多个预驱动器，每个相应的预驱动器耦合到所述多个片外驱动器中的一个，其中所述多个预驱动器被配置为导通所述芯片外驱动器; VREF测试板，用于向测试电路输入参考电压; 用于输出多个比较结果的多个输入缓冲器（IB），所述多个输入缓冲器中的每一个被配置为根据所述参考电压和所述TSV节点处的电压输出所述多个比较结果; 以及耦合到所述多个IB的测试焊盘，用于接收所述比较结果，以确定每个OCD的阻抗是否在期望的范围内。

32. 发明授权

US07863883B2 Low-voltage current reference and method thereof 有权
标题翻译：低压电流基准及其方法
公开(公告)号：US07863883B2
公开(公告)日：2011-01-04
申请号：US12105276
申请日：2008-04-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/30 , Y10S323/901
摘要： A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.
摘要翻译：提供电流与温度基本恒定的低电压电流基准包括低电压带隙，耦合到低电压带隙的启动电路以及耦合到低电压带隙和启动电路的电流加速器。低电压带隙用于提供恒定的电压基准，起动电路用于从非启动模式启动低电压带隙，并提供与绝对温度（PTAT）电流基准成正比。目前的夏天是根据恒定电压基准和PTAT电流参考值提供恒定的电流基准。

33. 发明申请

US20090261870A1 POWER-ON DETECTION CIRCUIT FOR DETECTING MINIMUM OPERATIONAL FREQUENCY 有权
标题翻译：用于检测最低运行频率的上电检测电路
公开(公告)号：US20090261870A1
公开(公告)日：2009-10-22
申请号：US12105280
申请日：2008-04-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： H03L7/00 , H03K3/03
CPC分类号： H03K3/0315
摘要： A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.
摘要翻译：用于检测最小工作频率的上电检测电路包括：振荡电路，包括：环形振荡器，用于产生第一振荡信号; 以及高通滤波器，用于对第一振荡信号进行滤波以产生第二振荡信号。上电检测电路还包括耦合到高通滤波器的整流装置，用于在第二振荡信号达到一定频率时产生逻辑信号。

34. 发明申请

US20090261801A1 LOW-VOLTAGE CURRENT REFERENCE AND METHOD THEREOF 有权
标题翻译：低电流电流参考及其方法
公开(公告)号：US20090261801A1
公开(公告)日：2009-10-22
申请号：US12105276
申请日：2008-04-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G05F3/28
CPC分类号： G05F3/30 , Y10S323/901
摘要： A low-voltage current reference providing a current being substantially constant with temperature includes a low voltage bandgap, a start circuit coupled to the low voltage bandgap, and a current summer coupled to the low voltage bandgap and to the start circuit. The low voltage bandgap is for providing a constant voltage reference, and the start circuit is for starting the low voltage bandgap from a non-start mode and for providing a proportional to absolute temperature (PTAT) current reference. The current summer is for providing a constant current reference according to the constant voltage reference and the PTAT current reference.
摘要翻译：提供电流与温度基本恒定的低电压电流基准包括低电压带隙，耦合到低电压带隙的启动电路以及耦合到低电压带隙和启动电路的电流加速器。低电压带隙用于提供恒定的电压基准，起动电路用于从非启动模式启动低电压带隙，并提供与绝对温度（PTAT）电流基准成正比。目前的夏天是根据恒定电压基准和PTAT电流参考值提供恒定的电流基准。

35. 发明申请

US20090195073A1 SYSTEM AND APPARATUS FOR GENERATING IDEAL RISE AND FALL TIME 有权
标题翻译：用于产生理想上升和下降时间的系统和装置
公开(公告)号：US20090195073A1
公开(公告)日：2009-08-06
申请号：US12025786
申请日：2008-02-05
申请人： Bret Roberts Dale , Darin James Daudelin , Ryan Andrew Jurasek , Dave Eugene Chapmen
发明人： Bret Roberts Dale , Darin James Daudelin , Ryan Andrew Jurasek , Dave Eugene Chapmen
IPC分类号： H02J1/00 , H02M3/06 , H02J7/00 , H02J3/00
CPC分类号： H03K19/00361 , Y10T307/50
摘要： A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.
摘要翻译：用于产生理想上升或下降时间的系统包括：用于提供第一电流的第一电流源; 耦合到第一电流源的可调电容分量，用于根据由比较信号控制的总电容产生输出信号; 耦合到可调电容部件的信号转换电路，用于当输出信号的电压电平达到参考值以便产生类似时钟的信号时，将存储在可调电容部件中的电荷恢复到预定值; 以及耦合到信号转换电路和可调电容分量的比较电路，用于将时钟状信号的周期与参考时钟信号的参考周期进行比较，并产生比较信号，以调节可调电容的总电容时间段不一样的组件。

36. 发明授权

US07750684B2 Power-on detection circuit for detecting minimum operational frequency 有权
标题翻译：用于检测最小工作频率的上电检测电路
公开(公告)号：US07750684B2
公开(公告)日：2010-07-06
申请号：US12105280
申请日：2008-04-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： H03K3/0315
摘要： A power-on detection circuit for detecting a minimum operational frequency includes: an oscillating circuit, which includes: a ring oscillator, for generating a first oscillating signal; and a high pass filter for filtering the first oscillating signal to generate a second oscillating signal. The power-on detection circuit also includes a rectification device, coupled to the high pass filter, for generating a logic signal once the second oscillating signal reaches a certain frequency.
摘要翻译：用于检测最小工作频率的上电检测电路包括：振荡电路，包括：环形振荡器，用于产生第一振荡信号; 以及高通滤波器，用于对第一振荡信号进行滤波以产生第二振荡信号。上电检测电路还包括耦合到高通滤波器的整流装置，用于在第二振荡信号达到一定频率时产生逻辑信号。

37. 发明申请

US20090237146A1 Dynamic Voltage Pump Circuit and Method of Dynamically Generating an Output Supply Voltage Thereof 有权
标题翻译：动态电压泵电路及动态产生输出电源电压的方法
公开(公告)号：US20090237146A1
公开(公告)日：2009-09-24
申请号：US12050178
申请日：2008-03-18
申请人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
发明人： Ryan Andrew Jurasek , Bret Roberts Dale , Darin James Daudelin , Dave Eugene Chapmen
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , H02M2001/007
摘要： A dynamic voltage pump circuit includes a first stage voltage pump, a second stage voltage pump, a limiter, and a comparator. The first stage voltage pump generates an intermediate supply voltage according to an input supply voltage and a pump signal. The second stage voltage pump generates an output supply voltage according to the intermediate supply voltage, the pump signal, and an enable signal; the second stage voltage pump is enabled and disabled when the enable signal is asserted and de-asserted, respectively. The limiter controls the pump signal according to a comparison of the output supply voltage with a first reference voltage. The comparator compares the first reference voltage with a second reference voltage to generate the enable signal, and can assert the enable signal when the desired output supply voltage exceeds the maximum possible intermediate supply voltage generated by the first stage voltage pump.
摘要翻译：动态电压泵电路包括第一级电压泵，第二级电压泵，限幅器和比较器。第一级电压泵根据输入电源电压和泵浦信号产生中间电源电压。第二级电压泵根据中间电源电压，泵浦信号和使能信号产生输出电源电压; 当使能信号分别被断言和解除置位时，第二级电压泵被使能和禁止。根据输出电源电压与第一参考电压的比较，限幅器控制泵浦信号。比较器将第一参考电压与第二参考电压进行比较以产生使能信号，并且当期望的输出电源电压超过由第一级电压泵产生的最大可能的中间电源电压时，可以断言使能信号。

38. 发明授权

US07622972B2 System and apparatus for generating ideal rise and fall time 有权
标题翻译：用于产生理想上升和下降时间的系统和装置
公开(公告)号：US07622972B2
公开(公告)日：2009-11-24
申请号：US12025786
申请日：2008-02-05
申请人： Bret Roberts Dale , Darin James Daudelin , Ryan Andrew Jurasek , Dave Eugene Chapmen
发明人： Bret Roberts Dale , Darin James Daudelin , Ryan Andrew Jurasek , Dave Eugene Chapmen
IPC分类号： H03K5/12
CPC分类号： H03K19/00361 , Y10T307/50
摘要： A system for generating an ideal rise or fall time includes: a first current source, for providing a first current; an adjustable capacitive component, coupled to the first current source, for generating an output signal according to a total capacitance controlled by a comparison signal; a signal conversion circuit, coupled to the adjustable capacitive component, for restoring charges stored in the adjustable capacitive component to a predetermined value when a voltage level of the output signal reaches a reference value to generate a clock-like signal; and a comparison circuit, coupled to the signal conversion circuit and the adjustable capacitive component, for comparing a period of the clock-like signal with a reference period of a reference clock signal and generating the comparison signal to adjust the total capacitance of the adjustable capacitive component when periods are not the same.
摘要翻译：用于产生理想上升或下降时间的系统包括：用于提供第一电流的第一电流源; 耦合到第一电流源的可调电容分量，用于根据由比较信号控制的总电容产生输出信号; 耦合到可调电容部件的信号转换电路，用于当输出信号的电压电平达到参考值以便产生类似时钟的信号时，将存储在可调电容部件中的电荷恢复到预定值; 以及耦合到信号转换电路和可调电容分量的比较电路，用于将时钟状信号的周期与参考时钟信号的参考周期进行比较，并产生比较信号，以调节可调电容的总电容时间段不一样的组件。

39. 发明授权

US08780666B2 Decoupling capacitance calibration devices and methods for DRAM 有权
标题翻译：用于DRAM的去耦电容校准装置和方法
公开(公告)号：US08780666B2
公开(公告)日：2014-07-15
申请号：US13340691
申请日：2011-12-30
申请人： Darin James Daudelin , Bret Roberts Dale
发明人： Darin James Daudelin , Bret Roberts Dale
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/40 , G11C11/4074 , G11C29/021 , G11C29/028
摘要： A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.
摘要翻译：去耦电容（decap）校准装置包括多个并联去耦电容器，其被配置为在电源和逻辑电路之间的点处电连接到电源。多个电容器具有多个不同的电容值，并被配置为根据多个输入独立地导通或截止。解除校准电路被配置为响应于确定信号来更新多个输入。电压检测器被配置为检测多个电容器的输出处的电压，并将输出电压与参考电压进行比较。解叠度校准装置被配置为响应于电压比较而产生确定信号。

40. 发明申请

US20130170286A1 DECOUPLING CAPACITANCE CALIBRATION DEVICES AND METHODS FOR DRAM 有权
标题翻译：解耦电容校准装置及其方法
公开(公告)号：US20130170286A1
公开(公告)日：2013-07-04
申请号：US13340691
申请日：2011-12-30
申请人： Darin James Daudelin , Bret Roberts Dale
发明人： Darin James Daudelin , Bret Roberts Dale
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C11/40 , G11C11/4074 , G11C29/021 , G11C29/028
摘要： A decoupling capacitance (decap) calibration device includes a plurality of parallel decoupling capacitors configured to be electrically connected to a power supply at a point between the power supply and logic circuitry. The plurality of capacitors exhibit a plurality of different capacitance values and are configured to independently turn on or off according to a plurality of inputs. Decap calibration circuitry is configured to update the plurality of inputs in response to a determination signal. A voltage detector is configured to detect a voltage at an output of the plurality of capacitors and to compare the output voltage to a reference voltage. The decap calibration device is configured to generate the determination signal in response to the voltage comparison.
摘要翻译：去耦电容（decap）校准装置包括多个并联去耦电容器，其被配置为在电源和逻辑电路之间的点处电连接到电源。多个电容器具有多个不同的电容值，并被配置为根据多个输入独立地导通或截止。解除校准电路被配置为响应于确定信号来更新多个输入。电压检测器被配置为检测多个电容器的输出处的电压，并将输出电压与参考电压进行比较。解叠度校准装置被配置为响应于电压比较而产生确定信号。

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