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31. 发明申请

US20140306949A1 SCALABLE GEOMETRY PROCESSING WITHIN A CHECKERBOARD MULTI-GPU CONFIGURATION 有权
标题翻译：在检查板多GPU配置中进行可扩展的几何处理
公开(公告)号：US20140306949A1
公开(公告)日：2014-10-16
申请号：US13976843
申请日：2011-11-18
申请人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
发明人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
IPC分类号： G06T1/20 , G06T15/10 , G06T15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
摘要翻译：描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器的核心，并将几何设置处理结果存储在本地存储中。然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果以及至少一个其他处理器核心的本地存储来执行光栅化。

32. 发明申请

US20140139512A1 Recording the Results of Visibility Tests at the Input Geometry Object Granularity 有权
标题翻译：记录输入几何对象粒度的可见性测试结果
公开(公告)号：US20140139512A1
公开(公告)日：2014-05-22
申请号：US13682967
申请日：2012-11-21
申请人： Thomas A. Piazza , Bimal Poddar , Peter L. Doyle
发明人： Thomas A. Piazza , Bimal Poddar , Peter L. Doyle
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T15/40
摘要： According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.
摘要翻译：根据本发明的一些实施例，可以通过执行深度测试并将结果记录在输入几何对象的粒度上来改善像素吞吐量。输入几何对象是由基元表示的描绘内的任何对象，例如输入三角形列表中的三角形或输入修补程序列表中的修补程序。

33. 发明授权

US06950108B2 Bandwidth reduction for rendering using vertex data 失效
标题翻译：使用顶点数据进行渲染的带宽减少
公开(公告)号：US06950108B2
公开(公告)日：2005-09-27
申请号：US10856054
申请日：2004-05-27
申请人： Peter L. Doyle , Thomas A. Piazza
发明人： Peter L. Doyle , Thomas A. Piazza
IPC分类号： G06T1/60 , G06T15/00 , G09G5/37 , G06F12/02
CPC分类号： G06T1/60 , G06T15/005
摘要： Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.
摘要翻译：本发明的实施例提供一种分割顶点缓冲器，其中每个顶点的数据在平行顶点缓冲器之间分割。第一个缓冲区包含顶点X和Y数据，而第二个并行缓冲区包含顶点数据的其余部分。给定分割顶点缓冲区，现在允许硬件分箱引擎读取和缓存顶点屏幕X和Y数据。特别是考虑到索引顶点参考之间通常具有高水平的时间一致性，大块顶点屏幕空间X和Y的读取和高速缓存导致硬件分档输入的存储器带宽的较低和高效利用。因此，本发明的实施例减少了硬件分组存储器带宽需求并提高了存储器利用率。

34. 发明授权

US06747657B2 Depth write disable for zone rendering 有权
公开(公告)号：US06747657B2
公开(公告)日：2004-06-08
申请号：US10038814
申请日：2001-12-31
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F1300
CPC分类号： G06T1/60 , G06T15/405
摘要： A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

35. 发明授权

US06738069B2 Efficient graphics state management for zone rendering 有权
标题翻译：区域渲染的高效图形状态管理
公开(公告)号：US06738069B2
公开(公告)日：2004-05-18
申请号：US10039007
申请日：2001-12-31
申请人： Peter L. Doyle
发明人： Peter L. Doyle
IPC分类号： G09G536
CPC分类号： G06T15/005
摘要： The present invention provides a mechanism to track and manage graphics state with hardware state-binning logic for use with the tile-based zone rendering method of generating graphical images. Only the current values of the dynamic state variables are maintained in hardware. Dynamic includes, but is not limited to, state variables that are considered likely to change between primitives. The set of dynamic state variables is subdivided into subgroups. Each state group is associated with a per-bin array of tracking bits. Whenever a state change is encountered, the tracking bit corresponding to the associated state group is set for all bins. Prior to placing a primitive in a bin, the tracking bits associated with that bin are examined, and the current state corresponding to set tracking bits is inserted in the bin before the primitive. Then the tracking bits for that bin are cleared.
摘要翻译：本发明提供一种用于利用硬件状态分级逻辑来跟踪和管理图形状态的机制，以用于生成图形图像的基于瓦片的区域渲染方法。只有硬件中维护动态状态变量的当前值。动态包括但不限于被认为可能在原语之间变化的状态变量。一组动态状态变量被细分为子组。每个状态组与跟踪位的每个二进制数组相关联。每当遇到状态改变时，对应于相关联的状态组的跟踪位都设置为所有存储区。在将原语放在一个bin之前，检查与该bin相关联的跟踪位，并将与设置的跟踪位对应的当前状态插入到该原语前的bin中。然后清除该仓的跟踪位。

36. 发明授权

US06429873B1 Addressing of monolithic texture maps 有权
标题翻译：解决单片纹理贴图
公开(公告)号：US06429873B1
公开(公告)日：2002-08-06
申请号：US09474182
申请日：1999-12-29
申请人： Nicolas I. Kacevas , Val G. Cook , Peter L. Doyle
发明人： Nicolas I. Kacevas , Val G. Cook , Peter L. Doyle
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： A method and circuit for determining the address of texture maps in memory, when only the base address of the primary texture map is known. The various maps associated with a given texture are sized and stored in a manner that allows any texel in any of the maps to be located based on the map number and the base address of the primary map. A circuit is provided that determines the necessary addresses with minimal calculations.
摘要翻译：当只知道主纹理图的基地址时，用于确定存储器中纹理贴图的地址的方法和电路。与给定纹理相关联的各种地图的大小和存储方式允许根据地图编号和主地图的基地址来定位任何地图中的任何纹理。提供了一种电路，通过最少的计算确定必要的地址。

37. 发明授权

US5251322A Method of operating a computer graphics system including asynchronously traversing its nodes 失效
标题翻译：操作计算机图形系统的方法，包括异步遍历其节点
公开(公告)号：US5251322A
公开(公告)日：1993-10-05
申请号：US477151
申请日：1990-02-08
申请人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. DiPirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
发明人： Peter L. Doyle , John P. Ellenberger , Ellis O. Jones , David C. Carver , Steven D. DiPirro , Branko J. Gerovac , William P. Armstrong , Ellen S. Gibson , Raymond E. Shapiro , Kevin C. Rushforth , William C. Roach
IPC分类号： G06T17/00 , G06F3/14
CPC分类号： G06T17/00
摘要： A method and apparatus for operating a computer graphics system to perform a conditional test on a node in a graphics data structure during the traversal of the graphics data structure by a structure walker. The graphics system is operated to manipulate data contained in a memory to define a value for an operand that is to be tested. The system accesses the operand from the memory. A structure walker performs a test on the value of the operand during traversal of the graphics data structure. Depending upon the result of the test, the structure walker traverses one of several paths in the graphics data structure to create a graphics display.
摘要翻译：一种用于操作计算机图形系统以在结构步行者遍历图形数据结构期间对图形数据结构中的节点执行条件测试的方法和装置。操作图形系统来操纵包含在存储器中的数据以定义要测试的操作数的值。系统从内存中访问操作数。结构步行器在图形数据结构遍历期间对操作数的值进行测试。根据测试结果，结构助行器遍历图形数据结构中的几条路径之一，以创建图形显示。

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