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31. 发明授权

US07560976B2 Method of operating a semiconductor device and the semiconductor device 有权
标题翻译：操作半导体器件和半导体器件的方法
公开(公告)号：US07560976B2
公开(公告)日：2009-07-14
申请号：US11711615
申请日：2007-02-28
申请人： Seouk-Kyu Choi , Nam-Jong Kim , Il-Man Bae , Jong-Hyun Choi
发明人： Seouk-Kyu Choi , Nam-Jong Kim , Il-Man Bae , Jong-Hyun Choi
IPC分类号： H03K3/01
CPC分类号： G11C11/4085 , G11C7/06 , G11C11/4074 , G11C11/4091 , G11C2207/065 , G11C2207/2227
摘要： In one example embodiment, a speed circuit path includes inverter chains that are controllable to operate in a slower, low sub-threshold leakage current mode or a faster, higher sub-threshold leakage current mode depending on an operating mode of the semiconductor device. A non-speed circuit path includes inverter chains that operate to reduce sub-threshold leakage current regardless of an operating mode of the semiconductor device.
摘要翻译：在一个示例性实施例中，速度电路路径包括根据半导体器件的工作模式，可控制的工作在较慢的，低亚阈值泄漏电流模式或更快，更高的亚阈值泄漏电流模式的逆变器链。非速度电路路径包括用于减小子阈值泄漏电流的逆变器链，而与半导体器件的工作模式无关。

32. 发明授权

US07394711B2 Multi-port semiconductor memory device and method for accessing and refreshing the same 失效
标题翻译：多端口半导体存储器件及其访问和刷新方法
公开(公告)号：US07394711B2
公开(公告)日：2008-07-01
申请号：US11616846
申请日：2006-12-27
申请人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
发明人： Chi-Sung Oh , Ho-Cheol Lee , Nam-Jong Kim
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1075 , G11C8/10 , G11C8/12 , G11C11/40603 , G11C11/40618
摘要： A semiconductor memory device and a method therefor for changing an access right to access a shared memory area according to an external command and a refresh mode is provided. In one embodiment, the semiconductor memory device includes a plurality of input/output ports for inputting command signals for first or second mode refresh operation, a memory array divided into a plurality of different memory areas including a shared memory area that is accessible via at least two of the plurality of input/output ports, and a grant control block for assigning an access right to access the shared memory area in response to an external command signal. The grant control block may also generate grant control signals for preferentially assigning the access right to access the shared memory area to the input/output port for inputting the command signals for the first mode refresh operation.
摘要翻译：提供一种半导体存储器件及其方法，用于根据外部命令和刷新模式改变访问共享存储区域的访问权限。在一个实施例中，半导体存储器件包括用于输入用于第一或第二模式刷新操作的命令信号的多个输入/输出端口，被分成多个不同存储区域的存储器阵列，该存储器阵列包括至少可访问的共享存储器区域多个输入/输出端口中的两个，以及用于响应于外部命令信号分配访问共享存储器区域的访问权限的授权控制块。授权控制块还可以生成授权控制信号，用于优先地分配访问共享存储器区域的访问权限到输入/输出端口，以输入用于第一模式刷新操作的命令信号。

33. 发明申请

US20050280450A1 Power-up reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US20050280450A1
公开(公告)日：2005-12-22
申请号：US11117400
申请日：2005-04-29
申请人： Chang-Ho Shin , Nam-Jong Kim
发明人： Chang-Ho Shin , Nam-Jong Kim
IPC分类号： G11C5/14 , H03K17/00 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.
摘要翻译：上电复位电路，功耗降低。上电复位电路的电阻可以在上电操作期间进行调整。从而可以减少待机电流，这可能降低上电复位电路中的功耗。

34. 发明申请

US20050093617A1 Reference voltage generating circuit for integrated circuit 失效
标题翻译：用于集成电路的基准电压发生电路
公开(公告)号：US20050093617A1
公开(公告)日：2005-05-05
申请号：US10964016
申请日：2004-10-13
申请人： Young-Sun Min , Nam-Jong Kim
发明人： Young-Sun Min , Nam-Jong Kim
IPC分类号： G11C5/14 , G05F3/02 , G05F3/30
CPC分类号： G05F3/30
摘要： A reference voltage generating circuit has a power supply voltage node to which a driving power supply voltage is intermittently applied. The circuit includes; a first current mirror section including a first MOS transistor of a first conductivity type having a source terminal connected to the power supply voltage node and a gate terminal connected to a drain terminal as a reference voltage output node, and a second MOS transistor of the first conductivity type having a gate terminal connected to the gate terminal of the first MOS transistor of the first conductivity type and a source terminal connected to the power supply voltage node; a second current mirror section including a third MOS transistor of a second conductivity type having a drain terminal connected to the reference voltage output node and a source terminal connected to a first current path to which a first resistor and a first diode are serially connected, and a fourth MOS transistor of the second conductivity type having a gate terminal and a drain terminal connected to the gate terminal of the third MOS transistor of the second conductivity type in common and a source terminal connected to the second current path to which a second diode is serially connected; and a charge transporting section connected between the gate terminal of the first MOS transistor of the first conductivity type in the first current mirror section and the gate terminal of the fourth MOS transistor of the second conductivity type in the second current mirror section.
摘要翻译：参考电压产生电路具有间歇地施加驱动电源电压的电源电压节点。电路包括第一电流镜部分，包括具有连接到电源电压节点的源极端子的第一导电类型的第一MOS晶体管和连接到作为参考电压输出节点的漏极端子的栅极端子，以及第一MOS晶体管，导电类型，其栅极端子连接到第一导电类型的第一MOS晶体管的栅极端子和连接到电源电压节点的源极端子; 第二电流镜部分，包括具有连接到参考电压输出节点的漏极端子的第二导电类型的第三MOS晶体管和与第一电阻器和第一二极管串联连接的第一电流通路连接的源极端子;以及第二导电类型的第四MOS晶体管具有栅极端子和漏极端子，其连接到第二导电类型的第三MOS晶体管的栅极端子，以及连接到第二电流路径的源极端子，第二二极管串联; 以及电荷输送部，连接在第一电流镜部中的第一导电型的第一MOS晶体管的栅极端子与第二电流镜部的第二导电型的第四MOS晶体管的栅极端子之间。

35. 发明授权

US06323702B1 Integrated circuit devices having circuits therein for driving large signal line loads 失效
标题翻译：具有用于驱动大信号线负载的电路的集成电路器件
公开(公告)号：US06323702B1
公开(公告)日：2001-11-27
申请号：US09547583
申请日：2000-04-12
申请人： Kyu-chan Lee , Nam-jong Kim
发明人： Kyu-chan Lee , Nam-jong Kim
IPC分类号： H03K513
CPC分类号： B29C65/348 , B29C65/342 , B29C65/3464 , B29C65/3468 , B29C65/7802 , B29C66/02241 , B29C66/1142 , B29C66/301 , B29C66/5221 , B29C66/72523 , B29L2023/22 , B29L2024/00 , Y10S264/46 , Y10T156/1043 , Y10T156/1066 , B29C65/00
摘要： A signal line drive circuit for a semiconductor device includes a first driver having an input for receiving an input signal and an output, a second driver having an input connected to the output of the first driver and an output connected to a signal line, and a third driver having an input connected to the output of the first driver and an output connected to a point of the signal line. The point of the signal line is spaced from the output of the second driver such that a first load is present between the output of the second driver and the point of the signal line, and such that a second load is present between the point of the signal line and an output of the signal line. The first, second and third drivers each include at least one inverting buffer. The drive circuit reduces a delay time of a signal transmitted through the signal line, and improves the voltage-time slope of the transmitted signal.
摘要翻译：一种用于半导体器件的信号线驱动电路包括具有用于接收输入信号和输出的输入的第一驱动器，具有连接到第一驱动器的输出的输入端和连接到信号线的输出的第二驱动器，以及第三驱动器具有连接到第一驱动器的输出的输入端和连接到信号线点的输出。信号线的点与第二驱动器的输出间隔开，使得第二驱动器的输出端与信号线的点之间存在第一负载，并且使得第二负载存在于信号线和信号线的输出。第一，第二和第三驱动器每个包括至少一个反相缓冲器。驱动电路减少了通过信号线传输的信号的延迟时间，并且提高了发送信号的电压 - 时间斜率。

36. 发明授权

US06249483B1 Semiconductor memory device having a circuit for latching data from a data line of a data output path and a related data latching method 失效
标题翻译：具有用于锁存来自数据输出路径的数据线的数据的电路的半导体存储器件和相关的数据锁存方法
公开(公告)号：US06249483B1
公开(公告)日：2001-06-19
申请号：US09548017
申请日：2000-04-12
申请人： Nam-jong Kim
发明人： Nam-jong Kim
IPC分类号： G11C1140
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/22 , G11C2207/2281
摘要： A semiconductor memory device is provided, having a circuit for latching data on a data line of a data output path. A related data latching method for the semiconductor memory device is also provided. The synchronous semiconductor memory device includes sense amplifiers for sensing the data of the memory cells, a data output register for latching the data of the memory cells, data lines for connecting the sense amplifiers and the data output register to transmit the sensed data to the data output register, and a data line control circuit for generating a data latch signal that releases the latching of the data on the data line in response to a first rising edge of the clock signal synchronized with a read command, and latches the data on the data line in response to a second rising edge of the clock signal.
摘要翻译：提供了一种半导体存储器件，其具有用于将数据锁存在数据输出路径的数据线上的电路。还提供了一种用于半导体存储器件的相关数据锁存方法。同步半导体存储器件包括用于感测存储器单元的数据的读出放大器，用于锁存存储器单元的数据的数据输出寄存器，用于连接读出放大器的数据线和数据输出寄存器，以将检测到的数据传送到数据输出寄存器和用于产生数据锁存信号的数据线控制电路，该数据锁存信号响应于与读命令同步的时钟信号的第一上升沿，释放数据线上的数据锁存，并将数据锁存在数据上响应于时钟信号的第二上升沿。

37. 发明授权

US07317651B2 Anti-fuse circuit and anti-fusing method 失效
标题翻译：防熔丝电路和防熔方法
公开(公告)号：US07317651B2
公开(公告)日：2008-01-08
申请号：US11443307
申请日：2006-05-31
申请人： Nam-Jong Kim , Young-Sun Min
发明人： Nam-Jong Kim , Young-Sun Min
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18
摘要： An anti-fuse and an anti-fusing method are disclosed. An example embodiment of the present invention is directed to an anti-fuse circuit, including an anti-fuse receiving a first voltage, a pull-up transistor coupled between the anti-fuse and a first node, the pull-up transistor configured to pull up a voltage at the first node to the first voltage when the anti-fuse is in a given operation mode, a pull-down transistor configured to pull down the voltage at the first node to a second voltage in response to a pull-down control signal, the second voltage lower than the first voltage, a voltage level detector configured to compare a detection reference voltage level with a voltage level at the first node to generate a detection output signal and a pull-down control circuit configured to generate the pull-down control signal based on a fuse input signal and the detection output signal.
摘要翻译：公开了一种抗熔丝和抗融合方法。本发明的示例性实施例涉及一种抗熔丝电路，其包括接收第一电压的反熔丝，耦合在反熔丝和第一节点之间的上拉晶体管，所述上拉晶体管被配置为拉当所述反熔丝处于给定的操作模式时，将所述第一节点处的电压升高到所述第一电压，配置为响应于下拉控制将所述第一节点处的电压下拉到第二电压的下拉晶体管信号，所述第二电压低于所述第一电压;电压电平检测器，被配置为将检测参考电压电平与所述第一节点处的电压电平进行比较，以产生检测输出信号;以及下拉控制电路，基于保险丝输入信号和检测输出信号的下降控制信号。

38. 发明申请

US20070296488A1 Semiconductor integrated circuits 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20070296488A1
公开(公告)日：2007-12-27
申请号：US11812690
申请日：2007-06-21
申请人： Nam-Jong Kim
发明人： Nam-Jong Kim
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： A semiconductor integrated circuit includes a logic circuit, a first and second switching device and an equalizer. The logic circuit includes a first circuit connected between a power supply voltage and a ground voltage supply line, and a second circuit connected between a power supply voltage supply line and a ground voltage. The first and second switching devices are connected between the power supply voltage and the power supply voltage supply line and between the ground voltage and the ground voltage supply line, respectively. The equalizer is connected between the power supply voltage supply line and the ground voltage supply line, and configured to adjust voltages of the power supply voltage supply line and the ground voltage supply line to be the same during a standby operation.
摘要翻译：半导体集成电路包括逻辑电路，第一和第二开关器件和均衡器。逻辑电路包括连接在电源电压和接地电压供应线之间的第一电路，以及连接在电源电压供给线和接地电压之间的第二电路。第一和第二开关装置分别连接在电源电压和电源电压供应线之间，以及接地电压和接地电压供应线之间。均衡器连接在电源电压供给线和接地电压供给线之间，并且被配置为在备用操作期间将电源电压供给线和接地电压供给线的电压调整为相同。

39. 发明授权

US07295050B2 Power-up reset circuit with reduced power consumption 失效
标题翻译：上电复位电路，功耗降低
公开(公告)号：US07295050B2
公开(公告)日：2007-11-13
申请号：US11117400
申请日：2005-04-29
申请人： Chang-Ho Shin , Nam-Jong Kim
发明人： Chang-Ho Shin , Nam-Jong Kim
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , H03K2217/0036
摘要： A power-up reset circuit with reduced power consumption. The resistance of the power-up reset circuit may be adjusted during a power-up operation. The standby current may thereby be reduced, which may reduce the power consumption in the power-up reset circuit.
摘要翻译：上电复位电路，功耗降低。上电复位电路的电阻可以在上电操作期间进行调整。从而可以减少待机电流，这可能降低上电复位电路中的功耗。

40. 发明授权

US07248075B2 Level shifter with low leakage current 失效
标题翻译：电平移位器具有低漏电流
公开(公告)号：US07248075B2
公开(公告)日：2007-07-24
申请号：US11020252
申请日：2004-12-27
申请人： Young-Sun Min , Nam-Jong Kim
发明人： Young-Sun Min , Nam-Jong Kim
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K3/356113 , H03K3/012
摘要： A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow Vcc and VOlow
摘要翻译：电压电平移位电路包括第一级，其接收具有电压电平Vcc和Vss的输入信号，其中Vcc> Vss，并且其输出互补的第一和第二中间信号，其中互补的第一和第二中间信号具有电压电平VI _{高和VI _{低，其中VI高低> VI _{以及第二级，其接收所述第一和第二中间信号，并且输出互补的第一和第二输出信号，其中所述互补的第一和第二输出信号具有电压电平VO高电平和VO < / SUB>，其中VO VO _{低，其中VI高的低 Vcc和VO低}}}}

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