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    • 32. 发明申请
    • Organic EL display device
    • 有机EL显示装置
    • US20080136339A1
    • 2008-06-12
    • US11984161
    • 2007-11-14
    • Toshiyuki MatsuuraMasahiro TanakaSukekazu ArataniMasao Shimizu
    • Toshiyuki MatsuuraMasahiro TanakaSukekazu ArataniMasao Shimizu
    • G09G3/00H01L51/54
    • H01L51/5052H01L27/3244H01L51/5234H01L2251/5315
    • The invention allows a top-emission-type organic EL display device to use a chemically stable conductive film containing ITO for forming a lower electrode of an organic EL layer. The organic EL layer includes an electron injection layer, an electron transport layer, a light emission layer, a hole transport layer and a hole injection layer. An upper electrode which constitutes a transparent electrode is formed of an IZO film. A lower electrode adopts the two-layered structure consisting of a lower layer made of Al or an Al alloy having high reflectance and an upper layer formed of a chemically stable ITO film. To enable the injection of electrons from the ITO film which constitutes the lower electrode, the electron injection layer is formed using a film which is acquired by co-depositing Li and Alq3 at a molecular ratio of 3:1. Due to such a constitution, electrons can be injected from the ITO film thus realizing the top-emission-type organic EL display device.
    • 本发明允许顶部发射型有机EL显示装置使用含有ITO的化学稳定的导电膜来形成有机EL层的下电极。 有机EL层包括电子注入层,电子传输层,发光层,空穴传输层和空穴注入层。 构成透明电极的上电极由IZO膜形成。 下电极采用由具有高反射率的Al或Al合金制成的下层和由化学稳定的ITO膜形成的上层构成的双层结构。 为了能够从构成下电极的ITO膜注入电子,使用通过以3:1的分子比共沉积Li和Alq3而获得的膜形成电子注入层。 由于这样的结构,可以从ITO膜注入电子,从而实现顶部发射型有机EL显示装置。
    • 37. 发明授权
    • Dc-DC converter
    • Dc-DC转换器
    • US07324355B2
    • 2008-01-29
    • US11647241
    • 2006-12-29
    • Kazuyuki IwamotoMasahiro Tanaka
    • Kazuyuki IwamotoMasahiro Tanaka
    • H02M3/335G05F1/56
    • H02M3/158H02M3/155H03K17/0814
    • A DC-DC converter is provided which includes a switching element, a choke coil, a flywheel diode, an output capacitor, a diode, and an auxiliary transformer having primary and secondary windings. The primary winding and the switching element constitute a first series circuit such that one terminal of the primary winding is connected to the drain terminal of the switching element, and the secondary winding and the diode constitute a second series circuit such that one terminal of the secondary winding is connected to the cathode terminal of the diode, where the other terminal of the second winding is connected to the positive terminal of a DC power source, and the anode terminal of the diode is connected to the negative terminal of the DC power source.
    • 提供一种DC-DC转换器,其包括开关元件,扼流线圈,续流二极管,输出电容器,二极管和具有初级和次级绕组的辅助变压器。 初级绕组和开关元件构成第一串联电路,使得初级绕组的一个端子连接到开关元件的漏极端子,次级绕组和二极管构成第二串联电路,使得次级绕组的一个端子 绕组连接到二极管的阴极端子,其中第二绕组的另一个端子连接到直流电源的正极端子,二极管的阳极端子连接到直流电源的负极端子。
    • 39. 发明授权
    • Clock generating circuit and clock generating method
    • 时钟发生电路和时钟发生方法
    • US07215165B2
    • 2007-05-08
    • US11267152
    • 2005-11-07
    • Shinichi YamamotoKoji OkadaMasahiro Tanaka
    • Shinichi YamamotoKoji OkadaMasahiro Tanaka
    • H03L7/06
    • H03L7/081
    • The invention provides a clock generating circuit for generating a spectrum spread clock and carrying out high-speed and accurate phase control of a reference clock signal and an output clock signal, which is composed of compact circuits, and a method for generating the clock. The spectrum spread clock generating circuit 1 is provided with a phase comparator unit 10 that compares the reference clock signal CLKS with the internal clock signal in terms of a phase difference, and outputs a control current IC1 in compliance with the result of comparison; a clock generating unit 20 for generating an output clock signal CLKO; a phase difference signal modulating unit 30 for outputting a control current IC3; and a delay unit 40 for delaying the output clock in compliance with the control current IC3 and outputting the internal clock signal CLKN.
    • 本发明提供了一种用于产生频谱扩展时钟并执行由紧凑电路组成的参考时钟信号和输出时钟信号的高速和精确的相位控制的时钟产生电路和用于产生时钟的方法。 频谱扩展时钟发生电路1设置有相位比较器单元10,该相位比较器单元10根据相位差将参考时钟信号CLKS与内部时钟信号进行比较,并且输出符合比较结果的控制电流IC 1; 用于产生输出时钟信号CLKO的时钟产生单元20; 用于输出控制电流IC 3的相位差信号调制单元30; 以及延迟单元40,用于根据控制电流IC 3延迟输出时钟并输出内部时钟信号CLKN。