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31. 发明申请

US20090302897A1 Driver circuit having high reliability and performance and semiconductor memory device including the same 审中-公开
标题翻译：具有高可靠性和性能的驱动电路和包括该驱动电路的半导体存储器件
公开(公告)号：US20090302897A1
公开(公告)日：2009-12-10
申请号：US12457240
申请日：2009-06-04
申请人： Jin-Young Kim , Ki-Whan Song
发明人： Jin-Young Kim , Ki-Whan Song
IPC分类号： H03K3/00
CPC分类号： H03K19/018521 , G11C8/08 , G11C11/4085
摘要： Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node.
摘要翻译：示例实施例涉及包括驱动器电路的驱动器电路和半导体存储器件。驱动器电路包括上拉单元，其被配置为响应于输入信号将输出节点连接到第一电源电压，连接在输出节点和第一节点之间的接口单元，以响应地降低输出节点的电压以及被配置为将第一节点连接到第二电源电压的下拉单元。接口单元包括第一晶体管，其被配置为响应于控制信号将输出节点与第一节点连接，以及连接在输出节点和第一节点之间的第一电阻器。接口单元还可以包括串联连接在输出节点和第一节点之间的第二电阻器和第二晶体管。

32. 发明授权

US07619928B2 Semiconductor memory device including floating body memory cells and method of operating the same 有权
标题翻译：包括浮体存储单元的半导体存储器件及其操作方法
公开(公告)号：US07619928B2
公开(公告)日：2009-11-17
申请号：US11943653
申请日：2007-11-21
申请人： Duk-Ha Park , Ki-Whan Song , Jin-Young Kim
发明人： Duk-Ha Park , Ki-Whan Song , Jin-Young Kim
IPC分类号： G11C11/03
CPC分类号： G11C11/404 , G11C11/4076 , G11C2211/4016
摘要： A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source line to store data. A controller applies a first voltage to the common source line, a negative second voltage to the word line, a third voltage as a first sense enable control voltage and the first voltage as a second sense enable control voltage during a first write period of a write operation. The controller also applies a fourth voltage to the common source line and the first voltage to the word line during a second write period of the write operation. The sensing portion amplifies a bit line and an inverted bit line to the third voltage or the first voltage, respectively, during the first write period in response to the first and second sense enable control voltages.
摘要翻译：半导体存储器件包括具有浮体的第一和第二存储单元，每个浮体包括连接到字线的栅极和连接到公共源极线以存储数据的电极。控制器在写入的第一写入周期期间将第一电压施加到公共源极线，对字线施加负的第二电压，将第三电压作为第一感测使能控制电压施加第一电压，将第一电压作为第二感测使能控制电压操作。在写入操作的第二写入周期期间，控制器还向公共源极线施加第四电压并将第一电压施加到字线。响应于第一和第二感测使能控制电压，感测部分在第一写入周期期间分别将位线和反相位线放大到第三电压或第一电压。

33. 发明授权

US07595532B2 Semiconductor memory devices and methods of forming the same 失效
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US07595532B2
公开(公告)日：2009-09-29
申请号：US11649074
申请日：2007-01-03
申请人： Ki-Whan Song , Chang-Hyun Kim
发明人： Ki-Whan Song , Chang-Hyun Kim
IPC分类号： H01L27/01 , H01L29/792
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/10844 , H01L29/7841
摘要： A semiconductor memory device includes a semiconductor substrate including an insulating layer, a charge storage region of a first conductivity type on the insulating layer, and an insulating film on the insulating layer and surrounding the charge storage region. A body region of the first conductivity type is on an upper surface of the charge storage region, and a gate stack including a gate electrode and a gate insulating film is on the body region. A source region and a drain region of a second conductivity type are on opposite sides of the body region. The charge storage region extends further towards the semiconductor substrate than the source region and/or the drain region. Methods of forming semiconductor memory devices are also disclosed.
摘要翻译：半导体存储器件包括：半导体衬底，包括绝缘层，绝缘层上的第一导电类型的电荷存储区域和绝缘层上的绝缘膜并且围绕电荷存储区域。第一导电类型的体区在电荷存储区的上表面上，并且包括栅电极和栅极绝缘膜的栅堆叠在身体区域上。第二导电类型的源极区域和漏极区域在身体区域的相对侧上。电荷存储区域比源极区域和/或漏极区域进一步向着半导体衬底延伸。还公开了形成半导体存储器件的方法。

34. 发明授权

US07580314B2 Memory device having open bit line structure and method of sensing data therefrom 失效
标题翻译：具有开放位线结构的存储器件和从其感测数据的方法
公开(公告)号：US07580314B2
公开(公告)日：2009-08-25
申请号：US11649273
申请日：2007-01-04
申请人： Su-A Kim , Ki-Whan Song
发明人： Su-A Kim , Ki-Whan Song
IPC分类号： G11C8/00
CPC分类号： G11C7/18 , G11C7/02 , G11C7/12 , G11C11/4094 , G11C11/4097 , H01L27/10897
摘要： A memory device includes a plurality of memory blocks. Each memory block includes a plurality of bit lines, a plurality of word lines, a plurality of memory cells provided at intersections of the bit lines and word lines; a plurality of capacitors, and a plurality of sense amplifiers. Each sense amplifier has a first input and a second input. The first input is connected to a first bit line of a first one of the memory blocks and is coupled via one of the capacitors to a first bit line of a second one of the memory blocks. The second input of the input is connected to a second bit line of the second one of the memory blocks and is coupled via one of the capacitors to a second bit line of the first one of the memory blocks.
摘要翻译：存储器件包括多个存储器块。每个存储块包括多个位线，多个字线，设置在位线和字线的交点处的多个存储单元; 多个电容器和多个读出放大器。每个读出放大器具有第一输入和第二输入。第一输入端连接到第一个存储器块的第一位线，并通过一个电容器耦合到第二个存储器块的第一位线。输入的第二输入连接到第二存储器块的第二位线，并且经由电容器中的一个耦合到第一个存储器块的第二位线。

35. 发明申请

US20090207648A1 MULTI-LEVEL DYNAMIC MEMORY DEVICE 有权
标题翻译：多级动态存储器件
公开(公告)号：US20090207648A1
公开(公告)日：2009-08-20
申请号：US12364119
申请日：2009-02-02
申请人： Ki-whan Song
发明人： Ki-whan Song
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： G11C11/565 , G11C7/06 , G11C7/14 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2207/002
摘要： A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.
摘要翻译：多级动态存储器件包括被分成主位线对和子位线对的位线对，连接在主位线对之间和子位线之间的第一和第二读出放大器分别在主位对和子位对之间交叉耦合的对，第一和第二耦合电容器; 以及分别与第一和第二耦合电容器并联连接并且其电容由控制电压信号调节的第一和第二校正电容器。

36. 发明授权

US07525146B2 Nonvolatile semiconductor memory devices 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07525146B2
公开(公告)日：2009-04-28
申请号：US11520886
申请日：2006-09-14
申请人： Ki-whan Song , Byung-Gook Park
发明人： Ki-whan Song , Byung-Gook Park
IPC分类号： H01L29/94
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11568 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.
摘要翻译：非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个并且形成连接柱子并跨越字线上方的位线。

37. 发明申请

US20090035903A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090035903A1
公开(公告)日：2009-02-05
申请号：US12194343
申请日：2008-08-19
申请人： Chang-Woo Oh , Ki-Whan Song
发明人： Chang-Woo Oh , Ki-Whan Song
IPC分类号： H01L21/336
CPC分类号： H01L27/1203 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/785
摘要： Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
摘要翻译：公开了半导体器件及其制造方法。该器件设置在基板上，包括由第一和第二侧壁构成的鳍片，在鳍片的第一侧壁上以间隔物图案形成的第一栅极线和形成在第二栅极上的间隔物图案中的第二栅极线鳍的侧壁第一和第二杂质区域设置在翅片中。第一和第二杂质区彼此隔离并且在第一和第二栅极线之间的鳍中限定沟道区。

38. 发明申请

US20070146008A1 Semiconductor circuit comprising vertical transistor 审中-公开
标题翻译：半导体电路包括垂直晶体管
公开(公告)号：US20070146008A1
公开(公告)日：2007-06-28
申请号：US11581390
申请日：2006-10-17
申请人： Nam-Kyun Tak , Ki-Whan Song
发明人： Nam-Kyun Tak , Ki-Whan Song
IPC分类号： H03K19/094
CPC分类号： H03F3/45183 , H01L27/0207 , H01L27/10897 , H01L29/66666 , H03F3/195 , H03F3/45188 , H03F2203/45292 , H03F2203/45352
摘要： A semiconductor circuit comprising a vertical transistor is disclosed. A differential amplifier circuit comprises a pair of amplification transistors, wherein the pair of amplification transistors comprises a first amplification transistor adapted to receive, amplify, and output a differential input signal. The first amplification transistor is a first vertical transistor comprising a first top and a first bottom, and the first top is a first drain of the first vertical transistor and the first bottom is a first source of the first vertical transistor. The differential amplifier circuit further comprises a current source electrically disposed between the pair of amplification transistors and a second power supply to form a current path between a first power supply and the second power supply.
摘要翻译：公开了一种包括垂直晶体管的半导体电路。差分放大器电路包括一对放大晶体管，其中该对放大晶体管包括适于接收，放大和输出差分输入信号的第一放大晶体管。第一放大晶体管是包括第一顶部和第一底部的第一垂直晶体管，第一顶部是第一垂直晶体管的第一漏极，第一底部是第一垂直晶体管的第一源极。差分放大器电路还包括电气设置在一对放大晶体管之间的电流源和第二电源，以在第一电源和第二电源之间形成电流路径。

39. 发明申请

US20070140005A1 Multi-level dynamic memory device 有权
标题翻译：多级动态存储设备
公开(公告)号：US20070140005A1
公开(公告)日：2007-06-21
申请号：US11638002
申请日：2006-12-13
申请人： Ki-whan Song
发明人： Ki-whan Song
IPC分类号： G11C16/04 , G11C11/34 , G11C16/06
CPC分类号： G11C11/565 , G11C7/06 , G11C7/14 , G11C7/18 , G11C11/4091 , G11C11/4097 , G11C11/4099 , G11C2207/002
摘要： A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.
摘要翻译：多级动态存储器件包括被分成主位线对和子位线对的位线对，连接在主位线对之间和子位线之间的第一和第二读出放大器分别在主位对和子位对之间交叉耦合的对，第一和第二耦合电容器; 以及分别与第一和第二耦合电容器并联连接并且其电容由控制电压信号调节的第一和第二校正电容器。

40. 发明申请

US20070122979A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070122979A1
公开(公告)日：2007-05-31
申请号：US11604943
申请日：2006-11-28
申请人： Chang-Woo Oh , Ki-Whan Song
发明人： Chang-Woo Oh , Ki-Whan Song
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L27/1203 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/785
摘要： Disclosed is a semiconductor device and method of fabricating the same. The device is disposed on a substrate, including a fin constructed with first and second sidewalls, a first gate line formed in the pattern of spacer on the first sidewall of the fin, and a second gate line formed in the pattern of spacer on the second sidewall of the fin. First and second impurity regions are disposed in the fin. The first and second impurity regions are isolated from each other and define a channel region in the fin between the first and second gate lines.
摘要翻译：公开了半导体器件及其制造方法。该器件设置在基板上，包括由第一和第二侧壁构成的鳍片，在鳍片的第一侧壁上以间隔物图案形成的第一栅极线和形成在第二栅极上的间隔物图案中的第二栅极线鳍的侧壁第一和第二杂质区域设置在翅片中。第一和第二杂质区彼此隔离并且在第一和第二栅极线之间的鳍中限定沟道区。

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